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add support for 128 bit inputs on both x86-64 and x86-32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57709 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -7509,15 +7509,13 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
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case 'r': // GENERAL_REGS
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case 'R': // LEGACY_REGS
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case 'l': // INDEX_REGS
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if (VT == MVT::i64 && Subtarget->is64Bit())
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return std::make_pair(0U, X86::GR64RegisterClass);
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if (VT == MVT::i32 || VT == MVT::i64)
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return std::make_pair(0U, X86::GR32RegisterClass);
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else if (VT == MVT::i16)
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return std::make_pair(0U, X86::GR16RegisterClass);
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else if (VT == MVT::i8)
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if (VT == MVT::i8)
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return std::make_pair(0U, X86::GR8RegisterClass);
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break;
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if (VT == MVT::i16)
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return std::make_pair(0U, X86::GR16RegisterClass);
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if (VT == MVT::i32 || !Subtarget->is64Bit())
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return std::make_pair(0U, X86::GR32RegisterClass);
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return std::make_pair(0U, X86::GR64RegisterClass);
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case 'f': // FP Stack registers.
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// If SSE is enabled for this VT, use f80 to ensure the isel moves the
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// value to the correct fpstack register class.
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@ -7529,7 +7527,6 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
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case 'y': // MMX_REGS if MMX allowed.
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if (!Subtarget->hasMMX()) break;
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return std::make_pair(0U, X86::VR64RegisterClass);
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break;
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case 'Y': // SSE_REGS if SSE2 allowed
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if (!Subtarget->hasSSE2()) break;
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// FALL THROUGH.
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