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PowerPC: Mark some more patterns as isCodeGenOnly.

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A couple of recently introduced conditional branch patterns
also need to be marked as isCodeGenOnly since they cannot
be handled by the asm parser.

No change in generated code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179690 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ulrich Weigand 2013-04-17 17:19:05 +00:00
parent 8952d909a5
commit 1fb54cfb0a
2 changed files with 6 additions and 0 deletions
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3
lib/Target/PowerPC/PPCInstr64Bit.td
View File

@ -72,6 +72,7 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
Requires<[In64BitMode]>;
let isCodeGenOnly = 1 in
def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
"b${cond:cc}ctr ${cond:reg}", BrB, []>,
Requires<[In64BitMode]>;
@ -131,6 +132,8 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
"bctrl", BrB, [(PPCbctrl)]>,
Requires<[In64BitMode]>;
let isCodeGenOnly = 1 in
def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
"b${cond:cc}ctrl ${cond:reg}", BrB, []>,
Requires<[In64BitMode]>;

3
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -725,6 +725,7 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
let isCodeGenOnly = 1 in
def BCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
"b${cond:cc}ctr ${cond:reg}", BrB, []>;
}
@ -788,6 +789,8 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
"bctrl", BrB, [(PPCbctrl)]>,
Requires<[In32BitMode]>;
let isCodeGenOnly = 1 in
def BCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
"b${cond:cc}ctrl ${cond:reg}", BrB, []>;
}