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[TableGen] Remove ListInit::size() in favor of getSize() which does the same thing and is already used in most places. NFC.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237341 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2015-05-14 05:53:56 +00:00
parent bbf57b36bb
commit 1fbf73bae3
2 changed files with 2 additions and 3 deletions
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1
include/llvm/TableGen/Record.h
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@ -842,7 +842,6 @@ public:
inline const_iterator begin() const { return Values.begin(); } inline const_iterator begin() const { return Values.begin(); }
inline const_iterator end () const { return Values.end(); } inline const_iterator end () const { return Values.end(); }
inline size_t size () const { return Values.size(); }
inline bool empty() const { return Values.empty(); } inline bool empty() const { return Values.empty(); }
/// resolveListElementReference - This method is used to implement /// resolveListElementReference - This method is used to implement

4
utils/TableGen/CodeGenRegisters.cpp
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@ -676,7 +676,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
// Allocation order 0 is the full set. AltOrders provides others. // Allocation order 0 is the full set. AltOrders provides others.
const SetTheory::RecVec *Elements = RegBank.getSets().expand(R); const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
ListInit *AltOrders = R->getValueAsListInit("AltOrders"); ListInit *AltOrders = R->getValueAsListInit("AltOrders");
Orders.resize(1 + AltOrders->size()); Orders.resize(1 + AltOrders->getSize());
// Default allocation order always contains all registers. // Default allocation order always contains all registers.
for (unsigned i = 0, e = Elements->size(); i != e; ++i) { for (unsigned i = 0, e = Elements->size(); i != e; ++i) {
@ -689,7 +689,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
// Alternative allocation orders may be subsets. // Alternative allocation orders may be subsets.
SetTheory::RecSet Order; SetTheory::RecSet Order;
for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) { for (unsigned i = 0, e = AltOrders->getSize(); i != e; ++i) {
RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc()); RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc());
Orders[1 + i].append(Order.begin(), Order.end()); Orders[1 + i].append(Order.begin(), Order.end());
// Verify that all altorder members are regclass members. // Verify that all altorder members are regclass members.