6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-04-18 19:38:51 +00:00
Code Issues Projects Releases Wiki Activity

add some new instructions to the classifier. With this, we correctly insert

Browse Source 
a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26590 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-03-07 07:14:55 +00:00
parent 7ce64852e8
commit 2046371e70
1 changed files with 11 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
lib/Target/PowerPC/PPCHazardRecognizers.cpp
View File

@ -41,6 +41,7 @@ using namespace llvm;
// conditions, we insert no-op instructions when appropriate.
//
// FIXME: This is missing some significant cases:
// -1. Handle all of the instruction types in GetInstrType.
// 0. Handling of instructions that must be the first/last in a group.
// 1. Modeling of microcoded instructions.
// 2. Handling of cracked instructions.
@ -76,12 +77,18 @@ PPCHazardRecognizer970::GetInstrType(unsigned Opcode) {
case PPC::BLA:
return BR;
case PPC::LFS:
case PPC::LFD:
case PPC::LWZ:
case PPC::LFSX:
case PPC::LWZX:
return LSU_LD;
case PPC::STFD:
case PPC::STW:
return LSU_ST;
case PPC::FADDS:
case PPC::FCTIWZ:
case PPC::FRSP:
case PPC::FSUB:
return FPU;
}
@ -159,8 +166,11 @@ getHazardType(SDNode *Node) {
unsigned LoadSize;
switch (Opcode) {
default: assert(0 && "Unknown load!");
case PPC::LFSX:
case PPC::LFS:
case PPC::LWZX:
case PPC::LWZ: LoadSize = 4; break;
case PPC::LFD: LoadSize = 8; break;
}
if (isLoadOfStoredAddress(LoadSize,
@ -186,6 +196,7 @@ void PPCHazardRecognizer970::EmitInstruction(SDNode *Node) {
switch (Opcode) {
default: assert(0 && "Unknown store instruction!");
case PPC::STFD: StoreSize = 8; break;
case PPC::STW: StoreSize = 4; break;
}
}