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Simplify the interface to the schedulers, to not pass the selected heuristicin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26692 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -188,8 +188,8 @@ public:
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///
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class ScheduleDAGSimple : public ScheduleDAG {
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private:
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SchedHeuristics Heuristic; // Scheduling heuristic
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bool NoSched; // Just do a BFS schedule, nothing fancy
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bool NoItins; // Don't use itineraries?
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ResourceTally<unsigned> Tally; // Resource usage tally
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unsigned NSlots; // Total latency
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static const unsigned NotFound = ~0U; // Search marker
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@ -204,9 +204,9 @@ private:
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public:
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// Ctor.
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ScheduleDAGSimple(SchedHeuristics hstc, SelectionDAG &dag,
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ScheduleDAGSimple(bool noSched, bool noItins, SelectionDAG &dag,
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MachineBasicBlock *bb, const TargetMachine &tm)
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: ScheduleDAG(dag, bb, tm), Heuristic(hstc), Tally(), NSlots(0),
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: ScheduleDAG(dag, bb, tm), NoSched(noSched), NoItins(noItins), NSlots(0),
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NodeCount(0), HasGroups(false), Info(NULL), HeadNG(NULL), TailNG(NULL) {
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assert(&TII && "Target doesn't provide instr info?");
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assert(&MRI && "Target doesn't provide register info?");
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@ -591,7 +591,7 @@ void ScheduleDAGSimple::GatherSchedulingInfo() {
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SDNode *Node = NI->Node;
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// If there are itineraries and it is a machine instruction
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if (InstrItins.isEmpty() || Heuristic == simpleNoItinScheduling) {
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if (InstrItins.isEmpty() || NoItins) {
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// If machine opcode
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if (Node->isTargetOpcode()) {
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// Get return type to guess which processing unit
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@ -859,7 +859,7 @@ void ScheduleDAGSimple::Schedule() {
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IdentifyGroups();
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// Test to see if scheduling should occur
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bool ShouldSchedule = NodeCount > 3 && Heuristic != noScheduling;
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bool ShouldSchedule = NodeCount > 3 && !NoSched;
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// Don't waste time if is only entry and return
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if (ShouldSchedule) {
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// Get latency and resource requirements
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@ -899,8 +899,13 @@ void ScheduleDAGSimple::Schedule() {
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/// createSimpleDAGScheduler - This creates a simple two pass instruction
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/// scheduler.
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llvm::ScheduleDAG* llvm::createSimpleDAGScheduler(SchedHeuristics Heuristic,
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llvm::ScheduleDAG* llvm::createSimpleDAGScheduler(bool NoItins,
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SelectionDAG &DAG,
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MachineBasicBlock *BB) {
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return new ScheduleDAGSimple(Heuristic, DAG, BB, DAG.getTarget());
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return new ScheduleDAGSimple(false, NoItins, DAG, BB, DAG.getTarget());
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}
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llvm::ScheduleDAG* llvm::createBFS_DAGScheduler(SelectionDAG &DAG,
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MachineBasicBlock *BB) {
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return new ScheduleDAGSimple(true, false, DAG, BB, DAG.getTarget());
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}
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@ -57,6 +57,16 @@ static const bool ViewISelDAGs = 0;
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static const bool ViewSchedDAGs = 0;
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#endif
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// Scheduling heuristics
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enum SchedHeuristics {
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defaultScheduling, // Let the target specify its preference.
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noScheduling, // No scheduling, emit breadth first sequence.
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simpleScheduling, // Two pass, min. critical path, max. utilization.
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simpleNoItinScheduling, // Same as above exact using generic latency.
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listSchedulingBURR, // Bottom up reg reduction list scheduling.
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listSchedulingTD // Top-down list scheduler.
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};
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namespace {
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cl::opt<SchedHeuristics>
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ISHeuristic(
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@ -2444,9 +2454,13 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
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SL = createBURRListDAGScheduler(DAG, BB);
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break;
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case noScheduling:
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SL = createBFS_DAGScheduler(DAG, BB);
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break;
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case simpleScheduling:
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SL = createSimpleDAGScheduler(false, DAG, BB);
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break;
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case simpleNoItinScheduling:
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SL = createSimpleDAGScheduler(ISHeuristic, DAG, BB);
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SL = createSimpleDAGScheduler(true, DAG, BB);
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break;
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case listSchedulingBURR:
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SL = createBURRListDAGScheduler(DAG, BB);
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