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Simplify the interface to the schedulers, to not pass the selected heuristicin.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26692 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-03-10 07:49:12 +00:00
parent 37cb415eec
commit 20a4921791
2 changed files with 28 additions and 9 deletions
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21
lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
View File

@ -188,8 +188,8 @@ public:
/// ///
class ScheduleDAGSimple : public ScheduleDAG { class ScheduleDAGSimple : public ScheduleDAG {
private: private:
SchedHeuristics Heuristic; // Scheduling heuristic bool NoSched; // Just do a BFS schedule, nothing fancy
bool NoItins; // Don't use itineraries?
ResourceTally<unsigned> Tally; // Resource usage tally ResourceTally<unsigned> Tally; // Resource usage tally
unsigned NSlots; // Total latency unsigned NSlots; // Total latency
static const unsigned NotFound = ~0U; // Search marker static const unsigned NotFound = ~0U; // Search marker
@ -204,9 +204,9 @@ private:
public: public:
// Ctor. // Ctor.
ScheduleDAGSimple(SchedHeuristics hstc, SelectionDAG &dag, ScheduleDAGSimple(bool noSched, bool noItins, SelectionDAG &dag,
MachineBasicBlock *bb, const TargetMachine &tm) MachineBasicBlock *bb, const TargetMachine &tm)
: ScheduleDAG(dag, bb, tm), Heuristic(hstc), Tally(), NSlots(0), : ScheduleDAG(dag, bb, tm), NoSched(noSched), NoItins(noItins), NSlots(0),
NodeCount(0), HasGroups(false), Info(NULL), HeadNG(NULL), TailNG(NULL) { NodeCount(0), HasGroups(false), Info(NULL), HeadNG(NULL), TailNG(NULL) {
assert(&TII && "Target doesn't provide instr info?"); assert(&TII && "Target doesn't provide instr info?");
assert(&MRI && "Target doesn't provide register info?"); assert(&MRI && "Target doesn't provide register info?");
@ -591,7 +591,7 @@ void ScheduleDAGSimple::GatherSchedulingInfo() {
SDNode *Node = NI->Node; SDNode *Node = NI->Node;
// If there are itineraries and it is a machine instruction // If there are itineraries and it is a machine instruction
if (InstrItins.isEmpty() || Heuristic == simpleNoItinScheduling) { if (InstrItins.isEmpty() || NoItins) {
// If machine opcode // If machine opcode
if (Node->isTargetOpcode()) { if (Node->isTargetOpcode()) {
// Get return type to guess which processing unit // Get return type to guess which processing unit
@ -859,7 +859,7 @@ void ScheduleDAGSimple::Schedule() {
IdentifyGroups(); IdentifyGroups();
// Test to see if scheduling should occur // Test to see if scheduling should occur
bool ShouldSchedule = NodeCount > 3 && Heuristic != noScheduling; bool ShouldSchedule = NodeCount > 3 && !NoSched;
// Don't waste time if is only entry and return // Don't waste time if is only entry and return
if (ShouldSchedule) { if (ShouldSchedule) {
// Get latency and resource requirements // Get latency and resource requirements
@ -899,8 +899,13 @@ void ScheduleDAGSimple::Schedule() {
/// createSimpleDAGScheduler - This creates a simple two pass instruction /// createSimpleDAGScheduler - This creates a simple two pass instruction
/// scheduler. /// scheduler.
llvm::ScheduleDAG* llvm::createSimpleDAGScheduler(SchedHeuristics Heuristic, llvm::ScheduleDAG* llvm::createSimpleDAGScheduler(bool NoItins,
SelectionDAG &DAG, SelectionDAG &DAG,
MachineBasicBlock *BB) { MachineBasicBlock *BB) {
return new ScheduleDAGSimple(Heuristic, DAG, BB, DAG.getTarget()); return new ScheduleDAGSimple(false, NoItins, DAG, BB, DAG.getTarget());
}
llvm::ScheduleDAG* llvm::createBFS_DAGScheduler(SelectionDAG &DAG,
MachineBasicBlock *BB) {
return new ScheduleDAGSimple(true, false, DAG, BB, DAG.getTarget());
} }

16
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -57,6 +57,16 @@ static const bool ViewISelDAGs = 0;
static const bool ViewSchedDAGs = 0; static const bool ViewSchedDAGs = 0;
#endif #endif
// Scheduling heuristics
enum SchedHeuristics {
defaultScheduling, // Let the target specify its preference.
noScheduling, // No scheduling, emit breadth first sequence.
simpleScheduling, // Two pass, min. critical path, max. utilization.
simpleNoItinScheduling, // Same as above exact using generic latency.
listSchedulingBURR, // Bottom up reg reduction list scheduling.
listSchedulingTD // Top-down list scheduler.
};
namespace { namespace {
cl::opt<SchedHeuristics> cl::opt<SchedHeuristics>
ISHeuristic( ISHeuristic(
@ -2444,9 +2454,13 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
SL = createBURRListDAGScheduler(DAG, BB); SL = createBURRListDAGScheduler(DAG, BB);
break; break;
case noScheduling: case noScheduling:
SL = createBFS_DAGScheduler(DAG, BB);
break;
case simpleScheduling: case simpleScheduling:
SL = createSimpleDAGScheduler(false, DAG, BB);
break;
case simpleNoItinScheduling: case simpleNoItinScheduling:
SL = createSimpleDAGScheduler(ISHeuristic, DAG, BB); SL = createSimpleDAGScheduler(true, DAG, BB);
break; break;
case listSchedulingBURR: case listSchedulingBURR:
SL = createBURRListDAGScheduler(DAG, BB); SL = createBURRListDAGScheduler(DAG, BB);