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Fix a bogus check that prevented folding VECTOR_SHUFFLE to UNDEF; add an optimization to fold VECTOR_SHUFFLE to a zero vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37173 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1630,7 +1630,7 @@ bool X86::isSHUFPMask(SDNode *N) {
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return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
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}
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/// isCommutedSHUFP - Returns true if the shuffle mask is except
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/// isCommutedSHUFP - Returns true if the shuffle mask is exactly
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/// the reverse of what x86 shuffles want. x86 shuffles requires the lower
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/// half elements to come from vector 1 (which would equal the dest.) and
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/// the upper half to come from vector 2.
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@ -2188,7 +2188,7 @@ static bool isSplatVector(SDNode *N) {
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/// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
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/// to an undef.
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static bool isUndefShuffle(SDNode *N) {
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if (N->getOpcode() != ISD::BUILD_VECTOR)
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if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
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return false;
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SDOperand V1 = N->getOperand(0);
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@ -2208,6 +2208,61 @@ static bool isUndefShuffle(SDNode *N) {
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return true;
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}
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/// isZeroNode - Returns true if Elt is a constant zero or a floating point
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/// constant +0.0.
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static inline bool isZeroNode(SDOperand Elt) {
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return ((isa<ConstantSDNode>(Elt) &&
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cast<ConstantSDNode>(Elt)->getValue() == 0) ||
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(isa<ConstantFPSDNode>(Elt) &&
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cast<ConstantFPSDNode>(Elt)->isExactlyValue(0.0)));
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}
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/// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
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/// to an zero vector.
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static bool isZeroShuffle(SDNode *N) {
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if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
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return false;
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SDOperand V1 = N->getOperand(0);
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SDOperand V2 = N->getOperand(1);
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SDOperand Mask = N->getOperand(2);
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unsigned NumElems = Mask.getNumOperands();
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for (unsigned i = 0; i != NumElems; ++i) {
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SDOperand Arg = Mask.getOperand(i);
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if (Arg.getOpcode() != ISD::UNDEF) {
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unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
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if (Idx < NumElems) {
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unsigned Opc = V1.Val->getOpcode();
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if (Opc == ISD::UNDEF)
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continue;
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if (Opc != ISD::BUILD_VECTOR ||
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!isZeroNode(V1.Val->getOperand(Idx)))
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return false;
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} else if (Idx >= NumElems) {
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unsigned Opc = V2.Val->getOpcode();
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if (Opc == ISD::UNDEF)
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continue;
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if (Opc != ISD::BUILD_VECTOR ||
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!isZeroNode(V2.Val->getOperand(Idx - NumElems)))
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return false;
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}
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}
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}
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return true;
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}
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/// getZeroVector - Returns a vector of specified type with all zero elements.
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///
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static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
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assert(MVT::isVector(VT) && "Expected a vector type");
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unsigned NumElems = getVectorNumElements(VT);
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MVT::ValueType EVT = MVT::getVectorBaseType(VT);
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bool isFP = MVT::isFloatingPoint(EVT);
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SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT);
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SmallVector<SDOperand, 8> ZeroVec(NumElems, Zero);
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return DAG.getNode(ISD::BUILD_VECTOR, VT, &ZeroVec[0], ZeroVec.size());
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}
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/// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
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/// that point to V2 points to its first element.
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static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
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@ -2274,18 +2329,6 @@ static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
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return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
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}
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/// getZeroVector - Returns a vector of specified type with all zero elements.
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///
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static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
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assert(MVT::isVector(VT) && "Expected a vector type");
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unsigned NumElems = getVectorNumElements(VT);
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MVT::ValueType EVT = MVT::getVectorBaseType(VT);
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bool isFP = MVT::isFloatingPoint(EVT);
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SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT);
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SmallVector<SDOperand, 8> ZeroVec(NumElems, Zero);
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return DAG.getNode(ISD::BUILD_VECTOR, VT, &ZeroVec[0], ZeroVec.size());
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}
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/// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
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///
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static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
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@ -2307,17 +2350,8 @@ static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
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return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
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}
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/// isZeroNode - Returns true if Elt is a constant zero or a floating point
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/// constant +0.0.
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static inline bool isZeroNode(SDOperand Elt) {
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return ((isa<ConstantSDNode>(Elt) &&
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cast<ConstantSDNode>(Elt)->getValue() == 0) ||
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(isa<ConstantFPSDNode>(Elt) &&
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cast<ConstantFPSDNode>(Elt)->isExactlyValue(0.0)));
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}
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/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
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/// vector and zero or undef vector.
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/// vector of zero or undef vector.
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static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
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unsigned NumElems, unsigned Idx,
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bool isZero, SelectionDAG &DAG) {
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@ -2584,6 +2618,9 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
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if (isUndefShuffle(Op.Val))
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return DAG.getNode(ISD::UNDEF, VT);
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if (isZeroShuffle(Op.Val))
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return getZeroVector(VT, DAG);
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if (isSplatMask(PermMask.Val)) {
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if (NumElems <= 4) return Op;
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// Promote it to a v4i32 splat.
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