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Add support for encoding VDUP (ARM core register) instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107201 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-06-29 20:13:29 +00:00
parent 871dc240d0
commit 21773e716f
1 changed files with 17 additions and 0 deletions
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17
lib/Target/ARM/ARMCodeEmitter.cpp
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@ -141,6 +141,7 @@ namespace {
void emitMiscInstruction(const MachineInstr &MI);
void emitNEONLaneInstruction(const MachineInstr &MI);
void emitNEONDupInstruction(const MachineInstr &MI);
void emitNEON1RegModImmInstruction(const MachineInstr &MI);
void emitNEON2RegInstruction(const MachineInstr &MI);
void emitNEON3RegInstruction(const MachineInstr &MI);
@ -420,6 +421,9 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
case ARMII::NSetLnFrm:
emitNEONLaneInstruction(MI);
break;
case ARMII::NDupFrm:
emitNEONDupInstruction(MI);
break;
case ARMII::N1RegModImmFrm:
emitNEON1RegModImmInstruction(MI);
break;
@ -1638,6 +1642,19 @@ void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
emitWordLE(Binary);
}
void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
unsigned Binary = getBinaryCodeForInstr(MI);
// Set the conditional execution predicate
Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
unsigned RegT = MI.getOperand(1).getReg();
RegT = ARMRegisterInfo::getRegisterNumbering(RegT);
Binary |= (RegT << ARMII::RegRdShift);
Binary |= encodeNEONRn(MI, 0);
emitWordLE(Binary);
}
void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
unsigned Binary = getBinaryCodeForInstr(MI);
// Destination register is encoded in Dd.