mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108258 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
7a41599962
commit
218977b53e
@ -565,6 +565,7 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case ARMISD::CMPZ: return "ARMISD::CMPZ";
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case ARMISD::CMPFP: return "ARMISD::CMPFP";
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case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
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case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
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case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
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case ARMISD::CMOV: return "ARMISD::CMOV";
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case ARMISD::CNEG: return "ARMISD::CNEG";
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@ -2216,7 +2217,7 @@ static bool isFloatingPointZero(SDValue Op) {
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/// the given operands.
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SDValue
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ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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SDValue &ARMCC, SelectionDAG &DAG,
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SDValue &ARMcc, SelectionDAG &DAG,
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DebugLoc dl) const {
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if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
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unsigned C = RHSC->getZExtValue();
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@ -2268,48 +2269,14 @@ ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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CompareType = ARMISD::CMPZ;
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break;
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}
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ARMCC = DAG.getConstant(CondCode, MVT::i32);
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ARMcc = DAG.getConstant(CondCode, MVT::i32);
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return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
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}
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static bool canBitcastToInt(SDNode *Op) {
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return Op->hasOneUse() &&
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ISD::isNormalLoad(Op) &&
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Op->getValueType(0) == MVT::f32;
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}
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static SDValue bitcastToInt(SDValue Op, SelectionDAG &DAG) {
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if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
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return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
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Ld->getChain(), Ld->getBasePtr(),
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Ld->getSrcValue(), Ld->getSrcValueOffset(),
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Ld->isVolatile(), Ld->isNonTemporal(),
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Ld->getAlignment());
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llvm_unreachable("Unknown VFP cmp argument!");
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}
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/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
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SDValue
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ARMTargetLowering::getVFPCmp(SDValue &LHS, SDValue &RHS, ISD::CondCode CC,
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SDValue &ARMCC, SelectionDAG &DAG,
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ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
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DebugLoc dl) const {
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if (UnsafeFPMath && FiniteOnlyFPMath() &&
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(CC == ISD::SETEQ || CC == ISD::SETOEQ ||
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CC == ISD::SETNE || CC == ISD::SETUNE) &&
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canBitcastToInt(LHS.getNode()) && canBitcastToInt(RHS.getNode())) {
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// If unsafe fp math optimization is enabled and there are no othter uses of
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// the CMP operands, and the condition code is EQ oe NE, we can optimize it
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// to an integer comparison.
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if (CC == ISD::SETOEQ)
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CC = ISD::SETEQ;
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else if (CC == ISD::SETUNE)
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CC = ISD::SETNE;
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LHS = bitcastToInt(LHS, DAG);
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RHS = bitcastToInt(RHS, DAG);
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return getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
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}
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SDValue Cmp;
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if (!isFloatingPointZero(RHS))
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Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
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@ -2328,59 +2295,184 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
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DebugLoc dl = Op.getDebugLoc();
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if (LHS.getValueType() == MVT::i32) {
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SDValue ARMCC;
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SDValue ARMcc;
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SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
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SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
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return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
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SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
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return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
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}
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ARMCC::CondCodes CondCode, CondCode2;
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FPCCToARMCC(CC, CondCode, CondCode2);
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SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
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SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
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SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
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SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
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SDValue Cmp = getVFPCmp(LHS, RHS, CC, ARMCC, DAG, dl);
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SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
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ARMCC, CCR, Cmp);
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ARMcc, CCR, Cmp);
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if (CondCode2 != ARMCC::AL) {
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SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
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SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
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// FIXME: Needs another CMP because flag can have but one use.
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SDValue Cmp2 = getVFPCmp(LHS, RHS, CC, ARMCC2, DAG, dl);
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SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
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Result = DAG.getNode(ARMISD::CMOV, dl, VT,
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Result, TrueVal, ARMCC2, CCR, Cmp2);
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Result, TrueVal, ARMcc2, CCR, Cmp2);
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}
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return Result;
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}
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SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
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SDValue Chain = Op.getOperand(0);
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/// canChangeToInt - Given the fp compare operand, return true if it is suitable
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/// to morph to an integer compare sequence.
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static bool canChangeToInt(SDValue Op, bool &SeenZero,
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const ARMSubtarget *Subtarget) {
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SDNode *N = Op.getNode();
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if (!N->hasOneUse())
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// Otherwise it requires moving the value from fp to integer registers.
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return false;
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if (!N->getNumValues())
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return false;
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EVT VT = Op.getValueType();
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if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
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// f32 case is generally profitable. f64 case only makes sense when vcmpe +
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// vmrs are very slow, e.g. cortex-a8.
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return false;
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if (isFloatingPointZero(Op)) {
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SeenZero = true;
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return true;
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}
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return ISD::isNormalLoad(N);
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}
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static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
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if (isFloatingPointZero(Op))
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return DAG.getConstant(0, MVT::i32);
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if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
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return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
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Ld->getChain(), Ld->getBasePtr(),
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Ld->getSrcValue(), Ld->getSrcValueOffset(),
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Ld->isVolatile(), Ld->isNonTemporal(),
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Ld->getAlignment());
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llvm_unreachable("Unknown VFP cmp argument!");
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}
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static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
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SDValue &RetVal1, SDValue &RetVal2) {
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if (isFloatingPointZero(Op)) {
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RetVal1 = DAG.getConstant(0, MVT::i32);
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RetVal2 = DAG.getConstant(0, MVT::i32);
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return;
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}
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if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
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SDValue Ptr = Ld->getBasePtr();
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RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
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Ld->getChain(), Ptr,
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Ld->getSrcValue(), Ld->getSrcValueOffset(),
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Ld->isVolatile(), Ld->isNonTemporal(),
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Ld->getAlignment());
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EVT PtrType = Ptr.getValueType();
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unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
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SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
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PtrType, Ptr, DAG.getConstant(4, PtrType));
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RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
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Ld->getChain(), NewPtr,
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Ld->getSrcValue(), Ld->getSrcValueOffset() + 4,
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Ld->isVolatile(), Ld->isNonTemporal(),
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NewAlign);
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return;
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}
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llvm_unreachable("Unknown VFP cmp argument!");
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}
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/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
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/// f32 and even f64 comparisons to integer ones.
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SDValue
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ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
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SDValue Chain = Op.getOperand(0);
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
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SDValue LHS = Op.getOperand(2);
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SDValue RHS = Op.getOperand(3);
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SDValue Dest = Op.getOperand(4);
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SDValue LHS = Op.getOperand(2);
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SDValue RHS = Op.getOperand(3);
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SDValue Dest = Op.getOperand(4);
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DebugLoc dl = Op.getDebugLoc();
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bool SeenZero = false;
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if (canChangeToInt(LHS, SeenZero, Subtarget) &&
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canChangeToInt(RHS, SeenZero, Subtarget) &&
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// If one of the operand is zero, it's safe to ignore the NaN case.
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(FiniteOnlyFPMath() || SeenZero)) {
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// If unsafe fp math optimization is enabled and there are no othter uses of
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// the CMP operands, and the condition code is EQ oe NE, we can optimize it
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// to an integer comparison.
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if (CC == ISD::SETOEQ)
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CC = ISD::SETEQ;
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else if (CC == ISD::SETUNE)
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CC = ISD::SETNE;
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SDValue ARMcc;
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if (LHS.getValueType() == MVT::f32) {
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LHS = bitcastf32Toi32(LHS, DAG);
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RHS = bitcastf32Toi32(RHS, DAG);
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SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
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SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
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return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
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Chain, Dest, ARMcc, CCR, Cmp);
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}
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SDValue LHS1, LHS2;
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SDValue RHS1, RHS2;
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expandf64Toi32(LHS, DAG, LHS1, LHS2);
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expandf64Toi32(RHS, DAG, RHS1, RHS2);
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ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
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ARMcc = DAG.getConstant(CondCode, MVT::i32);
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SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
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SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
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return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
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}
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return SDValue();
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}
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SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
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SDValue Chain = Op.getOperand(0);
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
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SDValue LHS = Op.getOperand(2);
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SDValue RHS = Op.getOperand(3);
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SDValue Dest = Op.getOperand(4);
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DebugLoc dl = Op.getDebugLoc();
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if (LHS.getValueType() == MVT::i32) {
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SDValue ARMCC;
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SDValue ARMcc;
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SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
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SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
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SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
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return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
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Chain, Dest, ARMCC, CCR,Cmp);
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Chain, Dest, ARMcc, CCR, Cmp);
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}
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assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
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if (UnsafeFPMath &&
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(CC == ISD::SETEQ || CC == ISD::SETOEQ ||
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CC == ISD::SETNE || CC == ISD::SETUNE)) {
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SDValue Result = OptimizeVFPBrcond(Op, DAG);
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if (Result.getNode())
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return Result;
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}
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ARMCC::CondCodes CondCode, CondCode2;
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FPCCToARMCC(CC, CondCode, CondCode2);
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SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
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SDValue Cmp = getVFPCmp(LHS, RHS, CC, ARMCC, DAG, dl);
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SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
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SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
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SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
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SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
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SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
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SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
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SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
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if (CondCode2 != ARMCC::AL) {
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ARMCC = DAG.getConstant(CondCode2, MVT::i32);
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SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
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ARMcc = DAG.getConstant(CondCode2, MVT::i32);
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SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
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Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
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}
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return Res;
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@ -2469,12 +2561,11 @@ SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
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EVT VT = Op.getValueType();
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EVT SrcVT = Tmp1.getValueType();
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SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
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SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
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SDValue ARMcc = DAG.getConstant(ARMCC::LT, MVT::i32);
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SDValue FP0 = DAG.getConstantFP(0.0, SrcVT);
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SDValue Cmp = getVFPCmp(Tmp1, FP0,
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ISD::SETLT, ARMCC, DAG, dl);
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SDValue Cmp = getVFPCmp(Tmp1, FP0, DAG, dl);
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SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
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return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
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return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMcc, CCR, Cmp);
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}
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SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
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@ -2611,7 +2702,7 @@ SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
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SDValue ShOpLo = Op.getOperand(0);
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SDValue ShOpHi = Op.getOperand(1);
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SDValue ShAmt = Op.getOperand(2);
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SDValue ARMCC;
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SDValue ARMcc;
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unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
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assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
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@ -2627,9 +2718,9 @@ SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
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SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
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SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
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ARMCC, DAG, dl);
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ARMcc, DAG, dl);
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SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
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SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC,
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SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
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CCR, Cmp);
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SDValue Ops[2] = { Lo, Hi };
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@ -2647,7 +2738,7 @@ SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
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SDValue ShOpLo = Op.getOperand(0);
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SDValue ShOpHi = Op.getOperand(1);
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SDValue ShAmt = Op.getOperand(2);
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SDValue ARMCC;
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SDValue ARMcc;
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assert(Op.getOpcode() == ISD::SHL_PARTS);
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SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
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@ -2661,9 +2752,9 @@ SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
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SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
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SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
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SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
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ARMCC, DAG, dl);
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ARMcc, DAG, dl);
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SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
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SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMCC,
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SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
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CCR, Cmp);
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SDValue Ops[2] = { Lo, Hi };
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@ -3825,6 +3916,15 @@ ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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return BB;
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}
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static
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MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
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for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
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E = MBB->succ_end(); I != E; ++I)
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if (*I != Succ)
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return *I;
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llvm_unreachable("Expecting a BB with two successors!");
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}
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MachineBasicBlock *
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ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) const {
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@ -3941,6 +4041,46 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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return BB;
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}
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case ARM::BCCi64:
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case ARM::BCCZi64: {
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// Compare both parts that make up the double comparison separately for
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||||
// equality.
|
||||
bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
|
||||
|
||||
unsigned LHS1 = MI->getOperand(1).getReg();
|
||||
unsigned LHS2 = MI->getOperand(2).getReg();
|
||||
if (RHSisZero) {
|
||||
AddDefaultPred(BuildMI(BB, dl,
|
||||
TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
|
||||
.addReg(LHS1).addImm(0));
|
||||
BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
|
||||
.addReg(LHS2).addImm(0)
|
||||
.addImm(ARMCC::EQ).addReg(ARM::CPSR);
|
||||
} else {
|
||||
unsigned RHS1 = MI->getOperand(3).getReg();
|
||||
unsigned RHS2 = MI->getOperand(4).getReg();
|
||||
AddDefaultPred(BuildMI(BB, dl,
|
||||
TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
|
||||
.addReg(LHS1).addReg(RHS1));
|
||||
BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
|
||||
.addReg(LHS2).addReg(RHS2)
|
||||
.addImm(ARMCC::EQ).addReg(ARM::CPSR);
|
||||
}
|
||||
|
||||
MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
|
||||
MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
|
||||
if (MI->getOperand(0).getImm() == ARMCC::NE)
|
||||
std::swap(destMBB, exitMBB);
|
||||
|
||||
BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
|
||||
.addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
|
||||
BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
|
||||
.addMBB(exitMBB);
|
||||
|
||||
MI->eraseFromParent(); // The pseudo instruction is gone now.
|
||||
return BB;
|
||||
}
|
||||
|
||||
case ARM::tANDsp:
|
||||
case ARM::tADDspr_:
|
||||
case ARM::tSUBspi_:
|
||||
|
||||
@ -53,6 +53,8 @@ namespace llvm {
|
||||
CMOV, // ARM conditional move instructions.
|
||||
CNEG, // ARM conditional negate instructions.
|
||||
|
||||
BCC_i64,
|
||||
|
||||
RBIT, // ARM bitreverse instruction
|
||||
|
||||
FTOSI, // FP to sint within a FP register.
|
||||
@ -363,9 +365,11 @@ namespace llvm {
|
||||
DebugLoc dl, SelectionDAG &DAG) const;
|
||||
|
||||
SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
|
||||
SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl) const;
|
||||
SDValue getVFPCmp(SDValue &LHS, SDValue &RHS, ISD::CondCode CC,
|
||||
SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl) const;
|
||||
SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
|
||||
SDValue getVFPCmp(SDValue LHS, SDValue RHS,
|
||||
SelectionDAG &DAG, DebugLoc dl) const;
|
||||
|
||||
SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
|
||||
|
||||
MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
|
||||
MachineBasicBlock *BB,
|
||||
|
||||
@ -38,6 +38,12 @@ def SDT_ARMBr2JT : SDTypeProfile<0, 4,
|
||||
[SDTCisPtrTy<0>, SDTCisVT<1, i32>,
|
||||
SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
|
||||
|
||||
def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
|
||||
[SDTCisVT<0, i32>,
|
||||
SDTCisVT<1, i32>, SDTCisVT<2, i32>,
|
||||
SDTCisVT<3, i32>, SDTCisVT<4, i32>,
|
||||
SDTCisVT<5, OtherVT>]>;
|
||||
|
||||
def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
|
||||
|
||||
def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
|
||||
@ -90,6 +96,9 @@ def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
|
||||
def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
|
||||
[SDNPHasChain]>;
|
||||
|
||||
def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
|
||||
[SDNPHasChain]>;
|
||||
|
||||
def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
|
||||
[SDNPOutFlag]>;
|
||||
|
||||
@ -2279,6 +2288,22 @@ defm CMNz : AI1_cmp_irs<0b1011, "cmn",
|
||||
def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
|
||||
(CMNzri GPR:$src, so_imm_neg:$imm)>;
|
||||
|
||||
// Pseudo i64 compares for some floating point compares.
|
||||
let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
|
||||
Defs = [CPSR] in {
|
||||
def BCCi64 : PseudoInst<(outs),
|
||||
(ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
|
||||
IIC_Br,
|
||||
"${:comment} B\t$dst GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, imm:$cc",
|
||||
[(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
|
||||
|
||||
def BCCZi64 : PseudoInst<(outs),
|
||||
(ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst),
|
||||
IIC_Br,
|
||||
"${:comment} B\t$dst GPR:$lhs1, GPR:$lhs2, 0, 0, imm:$cc",
|
||||
[(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
|
||||
} // usesCustomInserter
|
||||
|
||||
|
||||
// Conditional moves
|
||||
// FIXME: should be able to write a pattern for ARMcmov, but can't use
|
||||
|
||||
@ -1,16 +1,24 @@
|
||||
; RUN: llc < %s -march=arm -mattr=+vfp2 -enable-unsafe-fp-math -enable-finite-only-fp-math | FileCheck %s
|
||||
; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math -enable-finite-only-fp-math | FileCheck -check-prefix=FINITE %s
|
||||
; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math | FileCheck -check-prefix=NAN %s
|
||||
; rdar://7461510
|
||||
|
||||
define arm_apcscc i32 @t1(float* %a, float* %b) nounwind {
|
||||
entry:
|
||||
; CHECK: t1:
|
||||
; CHECK-NOT: vldr
|
||||
; CHECK: ldr
|
||||
; CHECK: ldr
|
||||
; CHECK: cmp r0, r1
|
||||
; CHECK-NOT: vcmpe.f32
|
||||
; CHECK-NOT: vmrs
|
||||
; CHECK: beq
|
||||
; FINITE: t1:
|
||||
; FINITE-NOT: vldr
|
||||
; FINITE: ldr
|
||||
; FINITE: ldr
|
||||
; FINITE: cmp r0, r1
|
||||
; FINITE-NOT: vcmpe.f32
|
||||
; FINITE-NOT: vmrs
|
||||
; FINITE: beq
|
||||
|
||||
; NAN: t1:
|
||||
; NAN: vldr.32 s0,
|
||||
; NAN: vldr.32 s1,
|
||||
; NAN: vcmpe.f32 s1, s0
|
||||
; NAN: vmrs apsr_nzcv, fpscr
|
||||
; NAN: beq
|
||||
%0 = load float* %a
|
||||
%1 = load float* %b
|
||||
%2 = fcmp une float %0, %1
|
||||
@ -25,5 +33,50 @@ bb2:
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
define arm_apcscc i32 @t2(double* %a, double* %b) nounwind {
|
||||
entry:
|
||||
; FINITE: t2:
|
||||
; FINITE-NOT: vldr
|
||||
; FINITE: ldrd r0, [r0]
|
||||
; FINITE: cmp r0, #0
|
||||
; FINITE: cmpeq r1, #0
|
||||
; FINITE-NOT: vcmpe.f32
|
||||
; FINITE-NOT: vmrs
|
||||
; FINITE: bne
|
||||
%0 = load double* %a
|
||||
%1 = fcmp oeq double %0, 0.000000e+00
|
||||
br i1 %1, label %bb1, label %bb2
|
||||
|
||||
bb1:
|
||||
%2 = call i32 @bar()
|
||||
ret i32 %2
|
||||
|
||||
bb2:
|
||||
%3 = call i32 @foo()
|
||||
ret i32 %3
|
||||
}
|
||||
|
||||
define arm_apcscc i32 @t3(float* %a, float* %b) nounwind {
|
||||
entry:
|
||||
; FINITE: t3:
|
||||
; FINITE-NOT: vldr
|
||||
; FINITE: ldr r0, [r0]
|
||||
; FINITE: cmp r0, #0
|
||||
; FINITE-NOT: vcmpe.f32
|
||||
; FINITE-NOT: vmrs
|
||||
; FINITE: bne
|
||||
%0 = load float* %a
|
||||
%1 = fcmp oeq float %0, 0.000000e+00
|
||||
br i1 %1, label %bb1, label %bb2
|
||||
|
||||
bb1:
|
||||
%2 = call i32 @bar()
|
||||
ret i32 %2
|
||||
|
||||
bb2:
|
||||
%3 = call i32 @foo()
|
||||
ret i32 %3
|
||||
}
|
||||
|
||||
declare i32 @bar()
|
||||
declare i32 @foo()
|
||||
|
||||
Loading…
Reference in New Issue
Block a user