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Add some initial patterns to simple binary instructions, though they

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currently don't do anything.  This elides patterns for binary operators
that ping on the carry flag, since we don't model it yet.

This patch also removes PPC::SUB, because it is dead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23230 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-09-02 21:18:00 +00:00
parent 6fdcb250d5
commit 218a15d02c
2 changed files with 43 additions and 25 deletions
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13
lib/Target/PowerPC/PPCInstrFormats.td
View File

@ -424,12 +424,15 @@ class XSForm_1<bits<6> opcode, bits<9> xo, dag OL, string asmstr>
}
// 1.7.11 XO-Form
class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OL, string asmstr>
class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OL, string asmstr,
list<dag> pattern>
: I<opcode, OL, asmstr> {
bits<5> RT;
bits<5> RA;
bits<5> RB;
let Pattern = pattern;
bit RC = 0; // set by isDOT
let Inst{6-10} = RT;
@ -440,15 +443,9 @@ class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OL, string asmstr>
let Inst{31} = RC;
}
class XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OL, string asmstr>
: XOForm_1<opcode, xo, oe, OL, asmstr> {
let Inst{11-15} = RB;
let Inst{16-20} = RA;
}
class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
dag OL, string asmstr>
: XOForm_1<opcode, xo, oe, OL, asmstr> {
: XOForm_1<opcode, xo, oe, OL, asmstr, []> {
let RB = 0;
}

55
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -14,6 +14,15 @@
include "PowerPCInstrFormats.td"
def set;
def mul;
def udiv;
def sdiv;
def sub;
def add;
def mulhs;
def mulhu;
class isPPC64 { bit PPC64 = 1; }
class isVMX { bit VMX = 1; }
class isDOT {
@ -70,7 +79,7 @@ let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
def SELECT_CC_FP : Pseudo<(ops FPRC:$dst, CRRC:$cond, FPRC:$T, FPRC:$F,
i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
}
@ -364,35 +373,47 @@ def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
// XO-Form instructions. Arithmetic instructions that can set overflow bit
//
def ADD : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
"add $rT, $rA, $rB">;
"add $rT, $rA, $rB",
[(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
"addc $rT, $rA, $rB">;
"addc $rT, $rA, $rB",
[]>;
def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
"adde $rT, $rA, $rB">;
"adde $rT, $rA, $rB",
[]>;
def DIVD : XOForm_1<31, 489, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
"divd $rT, $rA, $rB">, isPPC64;
"divd $rT, $rA, $rB",
[]>, isPPC64;
def DIVDU : XOForm_1<31, 457, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
"divdu $rT, $rA, $rB">, isPPC64;
"divdu $rT, $rA, $rB",
[]>, isPPC64;
def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
"divw $rT, $rA, $rB">;
"divw $rT, $rA, $rB",
[(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
"divwu $rT, $rA, $rB">;
"divwu $rT, $rA, $rB",
[(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
"mulhw $rT, $rA, $rB">;
"mulhw $rT, $rA, $rB",
[(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
"mulhwu $rT, $rA, $rB">;
"mulhwu $rT, $rA, $rB",
[(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
def MULLD : XOForm_1<31, 233, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
"mulld $rT, $rA, $rB">, isPPC64;
"mulld $rT, $rA, $rB",
[]>, isPPC64;
def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
"mullw $rT, $rA, $rB">;
"mullw $rT, $rA, $rB",
[(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
"subf $rT, $rA, $rB">;
"subf $rT, $rA, $rB",
[(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
"subfc $rT, $rA, $rB">;
"subfc $rT, $rA, $rB",
[]>;
def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
"subfe $rT, $rA, $rB">;
def SUB : XOForm_1r<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
"sub $rT, $rA, $rB">;
"subfe $rT, $rA, $rB",
[]>;
def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
"addme $rT, $rA">;
def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),