6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-03-03 14:31:10 +00:00
Code Issues Projects Releases Wiki Activity

Implement matching constraints. We can now say things like this:

Browse Source 
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)

and get:

xyz r2, r3, r4, r2

note that the r2's are pinned together.  Yaay for 2-address instructions.

2342 ----------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25893 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-02-02 00:25:23 +00:00
parent 2f0eec6520
commit 2223aea6ed
1 changed files with 28 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

43
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -1232,6 +1232,7 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
for (unsigned i = 0, e = Constraints.size(); i != e; ++i) { for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!"); assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
std::string &ConstraintCode = Constraints[i].Codes[0]; std::string &ConstraintCode = Constraints[i].Codes[0];
std::vector<unsigned> Regs = std::vector<unsigned> Regs =
TLI.getRegForInlineAsmConstraint(ConstraintCode); TLI.getRegForInlineAsmConstraint(ConstraintCode);
if (Regs.size() != 1) continue; // Not assigned a fixed reg. if (Regs.size() != 1) continue; // Not assigned a fixed reg.
@ -1243,7 +1244,7 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
OutputRegs.insert(TheReg); OutputRegs.insert(TheReg);
// If this is an early-clobber output, it cannot be assigned to the same // If this is an early-clobber output, it cannot be assigned to the same
// value as the input reg. // value as the input reg.
if (Constraints[i].isEarlyClobber) if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
InputRegs.insert(TheReg); InputRegs.insert(TheReg);
break; break;
case InlineAsm::isClobber: case InlineAsm::isClobber:
@ -1263,7 +1264,6 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
std::string &ConstraintCode = Constraints[i].Codes[0]; std::string &ConstraintCode = Constraints[i].Codes[0];
switch (Constraints[i].Type) { switch (Constraints[i].Type) {
case InlineAsm::isOutput: { case InlineAsm::isOutput: {
// Copy the output from the appropriate register. // Copy the output from the appropriate register.
std::vector<unsigned> Regs = std::vector<unsigned> Regs =
TLI.getRegForInlineAsmConstraint(ConstraintCode); TLI.getRegForInlineAsmConstraint(ConstraintCode);
@ -1272,10 +1272,17 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
unsigned DestReg; unsigned DestReg;
if (Regs.size() == 1) if (Regs.size() == 1)
DestReg = Regs[0]; DestReg = Regs[0];
else else {
DestReg = GetAvailableRegister(true, Constraints[i].isEarlyClobber, bool UsesInputRegister = false;
// If this is an early-clobber output, or if there is an input
// constraint that matches this, we need to reserve the input register
// so no other inputs allocate to it.
if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
UsesInputRegister = true;
DestReg = GetAvailableRegister(true, UsesInputRegister,
Regs, OutputRegs, InputRegs); Regs, OutputRegs, InputRegs);
}
assert(DestReg && "Couldn't allocate output reg!"); assert(DestReg && "Couldn't allocate output reg!");
const Type *OpTy; const Type *OpTy;
@ -1307,17 +1314,23 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
Value *Operand = I.getOperand(OpNum); Value *Operand = I.getOperand(OpNum);
const Type *OpTy = Operand->getType(); const Type *OpTy = Operand->getType();
OpNum++; // Consumes a call operand. OpNum++; // Consumes a call operand.
// Copy the input into the appropriate register.
std::vector<unsigned> Regs =
TLI.getRegForInlineAsmConstraint(ConstraintCode);
unsigned SrcReg; unsigned SrcReg;
if (Regs.size() == 1) if (isdigit(ConstraintCode[0])) { // Matching constraint?
SrcReg = Regs[0]; // If this is required to match an output register we have already set,
else // just use its register.
SrcReg = GetAvailableRegister(false, true, Regs, unsigned OperandNo = atoi(ConstraintCode.c_str());
OutputRegs, InputRegs); SrcReg = cast<RegisterSDNode>(AsmNodeOperands[OperandNo*2+2])->getReg();
} else {
// Copy the input into the appropriate register.
std::vector<unsigned> Regs =
TLI.getRegForInlineAsmConstraint(ConstraintCode);
if (Regs.size() == 1)
SrcReg = Regs[0];
else
SrcReg = GetAvailableRegister(false, true, Regs,
OutputRegs, InputRegs);
}
assert(SrcReg && "Couldn't allocate input reg!"); assert(SrcReg && "Couldn't allocate input reg!");
Chain = DAG.getCopyToReg(Chain, SrcReg, getValue(Operand), Flag); Chain = DAG.getCopyToReg(Chain, SrcReg, getValue(Operand), Flag);