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Add LLVMContext argument to getSetCCResultType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -198,7 +198,7 @@ public:
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/// the condition operand of SELECT and BRCOND nodes. In the case of
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/// BRCOND the argument passed is MVT::Other since there are no other
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/// operands to get a type hint from.
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virtual EVT getSetCCResultType(EVT VT) const;
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virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
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/// getCmpLibcallReturnType - Return the ValueType for comparison
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/// libcalls. Comparions libcalls include floating point comparion calls,
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@ -335,6 +335,12 @@ namespace {
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if (!LegalTypes) return true;
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return TLI.isTypeLegal(VT);
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}
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/// getSetCCResultType - Convenience wrapper around
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/// TargetLowering::getSetCCResultType
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EVT getSetCCResultType(EVT VT) const {
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return TLI.getSetCCResultType(*DAG.getContext(), VT);
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}
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};
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}
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@ -2636,7 +2642,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
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(!LegalOperations ||
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(TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
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TLI.isOperationLegal(ISD::SETCC,
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TLI.getSetCCResultType(N0.getSimpleValueType())))))
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getSetCCResultType(N0.getSimpleValueType())))))
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return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
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LL, LR, Result);
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}
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@ -3148,7 +3154,7 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
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(!LegalOperations ||
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(TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
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TLI.isOperationLegal(ISD::SETCC,
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TLI.getSetCCResultType(N0.getValueType())))))
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getSetCCResultType(N0.getValueType())))))
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return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
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LL, LR, Result);
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}
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@ -4225,7 +4231,7 @@ SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
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return N2;
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// Determine if the condition we're dealing with is constant
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SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
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SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
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N0, N1, CC, N->getDebugLoc(), false);
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if (SCC.getNode()) AddToWorkList(SCC.getNode());
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@ -4508,7 +4514,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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// On some architectures (such as SSE/NEON/etc) the SETCC result type is
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// of the same size as the compared operands. Only optimize sext(setcc())
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// if this is the case.
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EVT SVT = TLI.getSetCCResultType(N0VT);
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EVT SVT = getSetCCResultType(N0VT);
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// We know that the # elements of the results is the same as the
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// # elements of the compare (and the # elements of the compare result
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@ -4542,10 +4548,10 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
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if (SCC.getNode()) return SCC;
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if (!VT.isVector() && (!LegalOperations ||
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TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))))
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TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(VT))))
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return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
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DAG.getSetCC(N->getDebugLoc(),
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TLI.getSetCCResultType(VT),
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getSetCCResultType(VT),
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N0.getOperand(0), N0.getOperand(1),
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cast<CondCodeSDNode>(N0.getOperand(2))->get()),
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NegOne, DAG.getConstant(0, VT));
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@ -6815,7 +6821,7 @@ SDValue DAGCombiner::visitBRCOND(SDNode *N) {
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cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
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SDValue SetCC =
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DAG.getSetCC(N->getDebugLoc(),
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TLI.getSetCCResultType(Op0.getValueType()),
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getSetCCResultType(Op0.getValueType()),
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Op0, DAG.getConstant(0, Op0.getValueType()),
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ISD::SETNE);
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@ -6885,7 +6891,7 @@ SDValue DAGCombiner::visitBRCOND(SDNode *N) {
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EVT SetCCVT = N1.getValueType();
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if (LegalTypes)
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SetCCVT = TLI.getSetCCResultType(SetCCVT);
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SetCCVT = getSetCCResultType(SetCCVT);
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SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
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SetCCVT,
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Op0, Op1,
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@ -6916,7 +6922,7 @@ SDValue DAGCombiner::visitBR_CC(SDNode *N) {
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// MachineBasicBlock CFG, which is awkward.
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// Use SimplifySetCC to simplify SETCC's.
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SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
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SDValue Simp = SimplifySetCC(getSetCCResultType(CondLHS.getValueType()),
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CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
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false);
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if (Simp.getNode()) AddToWorkList(Simp.getNode());
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@ -9737,7 +9743,7 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
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ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
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// Determine if the condition we're dealing with is constant
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SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
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SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
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N0, N1, CC, DL, false);
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if (SCC.getNode()) AddToWorkList(SCC.getNode());
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ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
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@ -9803,7 +9809,7 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
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SDValue One = DAG.getIntPtrConstant(EltSize);
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SDValue Cond = DAG.getSetCC(DL,
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TLI.getSetCCResultType(N0.getValueType()),
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getSetCCResultType(N0.getValueType()),
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N0, N1, CC);
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AddToWorkList(Cond.getNode());
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SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
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@ -9906,11 +9912,11 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
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// NOTE: Don't create a SETCC if it's not legal on this target.
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if (!LegalOperations ||
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TLI.isOperationLegal(ISD::SETCC,
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LegalTypes ? TLI.getSetCCResultType(N0.getValueType()) : MVT::i1)) {
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LegalTypes ? getSetCCResultType(N0.getValueType()) : MVT::i1)) {
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SDValue Temp, SCC;
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// cast from setcc result type to select result type
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if (LegalTypes) {
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SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
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SCC = DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()),
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N0, N1, CC);
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if (N2.getValueType().bitsLT(SCC.getValueType()))
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Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(),
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@ -9943,8 +9949,8 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
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if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
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EVT XType = N0.getValueType();
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if (!LegalOperations ||
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TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
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SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
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TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(XType))) {
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SDValue Res = DAG.getSetCC(DL, getSetCCResultType(XType), N0, N1, CC);
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if (Res.getValueType() != VT)
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Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
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return Res;
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@ -58,6 +58,10 @@ class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener {
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/// LegalizedNodes - The set of nodes which have already been legalized.
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SmallPtrSet<SDNode *, 16> LegalizedNodes;
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EVT getSetCCResultType(EVT VT) const {
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return TLI.getSetCCResultType(*DAG.getContext(), VT);
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}
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// Libcall insertion helpers.
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public:
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@ -1542,7 +1546,7 @@ SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
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}
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}
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// Now get the sign bit proper, by seeing whether the value is negative.
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SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
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SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
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SignBit, DAG.getConstant(0, SignBit.getValueType()),
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ISD::SETLT);
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// Get the absolute value of the result.
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@ -2327,7 +2331,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
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// select. We happen to get lucky and machinesink does the right
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// thing most of the time. This would be a good candidate for a
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//pseudo-op, or, even better, for whole-function isel.
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SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
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SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
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Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
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return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast);
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}
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@ -2340,10 +2344,10 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
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DAG.getConstant(UINT64_C(0x800), MVT::i64));
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SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
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DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
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SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
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SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
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And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
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SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
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SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
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SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
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Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
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ISD::SETUGE);
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SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
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@ -2365,7 +2369,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
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SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
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SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
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SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
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Op0, DAG.getConstant(0, Op0.getValueType()),
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ISD::SETLT);
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SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
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@ -2913,7 +2917,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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APInt x = APInt::getSignBit(NVT.getSizeInBits());
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(void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
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Tmp1 = DAG.getConstantFP(apf, VT);
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Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
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Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
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Node->getOperand(0),
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Tmp1, ISD::SETLT);
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True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
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@ -3131,7 +3135,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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EVT VT = Node->getValueType(0);
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Tmp1 = Node->getOperand(0);
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Tmp2 = DAG.getConstantFP(0.0, VT);
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Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
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Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
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Tmp1, Tmp2, ISD::SETUGT);
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Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
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Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
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@ -3528,10 +3532,10 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
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TLI.getShiftAmountTy(BottomHalf.getValueType()));
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Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
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TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
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TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
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ISD::SETNE);
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} else {
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TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
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TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
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DAG.getConstant(0, VT), ISD::SETNE);
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}
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Results.push_back(BottomHalf);
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@ -3654,7 +3658,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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Tmp4 = Node->getOperand(3); // False
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SDValue CC = Node->getOperand(4);
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LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
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LegalizeSetCCCondCode(getSetCCResultType(Tmp1.getValueType()),
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Tmp1, Tmp2, CC, dl);
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assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
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@ -3671,7 +3675,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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Tmp3 = Node->getOperand(3); // RHS
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Tmp4 = Node->getOperand(1); // CC
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LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
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LegalizeSetCCCondCode(getSetCCResultType(Tmp2.getValueType()),
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Tmp2, Tmp3, Tmp4, dl);
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assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
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@ -3753,7 +3757,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
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Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
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if (Node->getOpcode() == ISD::CTTZ) {
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// FIXME: This should set a bit in the zero extended value instead.
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Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
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Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
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Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
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ISD::SETEQ);
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Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
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@ -1293,14 +1293,14 @@ void DAGTypeLegalizer::FloatExpandSetCCOperands(SDValue &NewLHS,
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// FCMPU crN, lo1, lo2
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// The following can be improved, but not that much.
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SDValue Tmp1, Tmp2, Tmp3;
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Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
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Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
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LHSHi, RHSHi, ISD::SETOEQ);
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Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
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Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
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LHSLo, RHSLo, CCCode);
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Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
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Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
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Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
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LHSHi, RHSHi, ISD::SETUNE);
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Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
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Tmp2 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
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LHSHi, RHSHi, CCCode);
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Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
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NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3);
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@ -492,7 +492,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
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EVT OpTy = N->getOperand(1).getValueType();
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// Promote all the way up to the canonical SetCC type.
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Mask = PromoteTargetBoolean(Mask, TLI.getSetCCResultType(OpTy));
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Mask = PromoteTargetBoolean(Mask, getSetCCResultType(OpTy));
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SDValue LHS = GetPromotedInteger(N->getOperand(1));
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SDValue RHS = GetPromotedInteger(N->getOperand(2));
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return DAG.getNode(ISD::VSELECT, N->getDebugLoc(),
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@ -508,7 +508,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
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}
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SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
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EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
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EVT SVT = getSetCCResultType(N->getOperand(0).getValueType());
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EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
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@ -892,7 +892,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
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assert(OpNo == 1 && "only know how to promote condition");
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// Promote all the way up to the canonical SetCC type.
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EVT SVT = TLI.getSetCCResultType(MVT::Other);
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EVT SVT = getSetCCResultType(MVT::Other);
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SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
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// The chain (Op#0) and basic block destination (Op#2) are always legal types.
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@ -984,7 +984,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
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EVT OpTy = N->getOperand(1).getValueType();
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// Promote all the way up to the canonical SetCC type.
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EVT SVT = TLI.getSetCCResultType(N->getOpcode() == ISD::SELECT ?
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EVT SVT = getSetCCResultType(N->getOpcode() == ISD::SELECT ?
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OpTy.getScalarType() : OpTy);
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Cond = PromoteTargetBoolean(Cond, SVT);
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@ -1459,7 +1459,7 @@ ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
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SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
|
||||
SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
|
||||
SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
|
||||
SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
|
||||
SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
|
||||
Amt, NVBitsNode, ISD::SETULT);
|
||||
|
||||
SDValue LoS, HiS, LoL, HiL;
|
||||
@ -1556,12 +1556,12 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
|
||||
if (N->getOpcode() == ISD::ADD) {
|
||||
Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
|
||||
Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
|
||||
SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
|
||||
SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
|
||||
ISD::SETULT);
|
||||
SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
|
||||
DAG.getConstant(1, NVT),
|
||||
DAG.getConstant(0, NVT));
|
||||
SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
|
||||
SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
|
||||
ISD::SETULT);
|
||||
SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
|
||||
DAG.getConstant(1, NVT), Carry1);
|
||||
@ -1570,7 +1570,7 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
|
||||
Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
|
||||
Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
|
||||
SDValue Cmp =
|
||||
DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
|
||||
DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
|
||||
LoOps[0], LoOps[1], ISD::SETULT);
|
||||
SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
|
||||
DAG.getConstant(1, NVT),
|
||||
@ -1719,7 +1719,7 @@ void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
|
||||
GetExpandedInteger(N->getOperand(0), Lo, Hi);
|
||||
EVT NVT = Lo.getValueType();
|
||||
|
||||
SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
|
||||
SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
|
||||
DAG.getConstant(0, NVT), ISD::SETNE);
|
||||
|
||||
SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
|
||||
@ -1749,7 +1749,7 @@ void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
|
||||
GetExpandedInteger(N->getOperand(0), Lo, Hi);
|
||||
EVT NVT = Lo.getValueType();
|
||||
|
||||
SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
|
||||
SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
|
||||
DAG.getConstant(0, NVT), ISD::SETNE);
|
||||
|
||||
SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
|
||||
@ -2287,7 +2287,7 @@ void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
|
||||
|
||||
// A divide for UMULO will be faster than a function call. Select to
|
||||
// make sure we aren't using 0.
|
||||
SDValue isZero = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
|
||||
SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(VT),
|
||||
RHS, DAG.getConstant(0, VT), ISD::SETEQ);
|
||||
SDValue NotZero = DAG.getNode(ISD::SELECT, dl, VT, isZero,
|
||||
DAG.getConstant(1, VT), RHS);
|
||||
@ -2566,16 +2566,16 @@ void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
|
||||
// this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
|
||||
TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true, NULL);
|
||||
SDValue Tmp1, Tmp2;
|
||||
Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
|
||||
Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()),
|
||||
LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
|
||||
if (!Tmp1.getNode())
|
||||
Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
|
||||
Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
|
||||
LHSLo, RHSLo, LowCC);
|
||||
Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
|
||||
Tmp2 = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
|
||||
LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
|
||||
if (!Tmp2.getNode())
|
||||
Tmp2 = DAG.getNode(ISD::SETCC, dl,
|
||||
TLI.getSetCCResultType(LHSHi.getValueType()),
|
||||
getSetCCResultType(LHSHi.getValueType()),
|
||||
LHSHi, RHSHi, DAG.getCondCode(CCCode));
|
||||
|
||||
ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
|
||||
@ -2595,11 +2595,11 @@ void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
|
||||
return;
|
||||
}
|
||||
|
||||
NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
|
||||
NewLHS = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
|
||||
LHSHi, RHSHi, ISD::SETEQ, false,
|
||||
DagCombineInfo, dl);
|
||||
if (!NewLHS.getNode())
|
||||
NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
|
||||
NewLHS = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
|
||||
LHSHi, RHSHi, ISD::SETEQ);
|
||||
NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
|
||||
NewLHS, Tmp1, Tmp2);
|
||||
@ -2817,7 +2817,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
|
||||
SDValue Lo, Hi;
|
||||
GetExpandedInteger(Op, Lo, Hi);
|
||||
SDValue SignSet = DAG.getSetCC(dl,
|
||||
TLI.getSetCCResultType(Hi.getValueType()),
|
||||
getSetCCResultType(Hi.getValueType()),
|
||||
Hi, DAG.getConstant(0, Hi.getValueType()),
|
||||
ISD::SETLT);
|
||||
|
||||
|
@ -73,6 +73,10 @@ private:
|
||||
return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal;
|
||||
}
|
||||
|
||||
EVT getSetCCResultType(EVT VT) const {
|
||||
return TLI.getSetCCResultType(*DAG.getContext(), VT);
|
||||
}
|
||||
|
||||
/// IgnoreNodeResults - Pretend all of this node's results are legal.
|
||||
bool IgnoreNodeResults(SDNode *N) const {
|
||||
return N->getOpcode() == ISD::TargetConstant;
|
||||
|
@ -597,7 +597,7 @@ SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
|
||||
return DAG.UnrollVectorOp(Op.getNode());
|
||||
|
||||
// Generate a mask operand.
|
||||
EVT MaskTy = TLI.getSetCCResultType(VT);
|
||||
EVT MaskTy = TLI.getSetCCResultType(*DAG.getContext(), VT);
|
||||
assert(MaskTy.isVector() && "Invalid CC type");
|
||||
assert(MaskTy.getSizeInBits() == Op1.getValueType().getSizeInBits()
|
||||
&& "Invalid mask size");
|
||||
@ -758,7 +758,8 @@ SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
|
||||
DAG.getIntPtrConstant(i));
|
||||
SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
|
||||
DAG.getIntPtrConstant(i));
|
||||
Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
|
||||
Ops[i] = DAG.getNode(ISD::SETCC, dl,
|
||||
TLI.getSetCCResultType(*DAG.getContext(), TmpEltVT),
|
||||
LHSElem, RHSElem, CC);
|
||||
Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i],
|
||||
DAG.getConstant(APInt::getAllOnesValue
|
||||
|
@ -2385,7 +2385,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
|
||||
|
||||
// Get a new SETCC node to compare the newly widened operands.
|
||||
// Only some of the compared elements are legal.
|
||||
EVT SVT = TLI.getSetCCResultType(InOp0.getValueType());
|
||||
EVT SVT = TLI.getSetCCResultType(*DAG.getContext(), InOp0.getValueType());
|
||||
SDValue WideSETCC = DAG.getNode(ISD::SETCC, N->getDebugLoc(),
|
||||
SVT, InOp0, InOp1, N->getOperand(2));
|
||||
|
||||
|
@ -1710,8 +1710,10 @@ void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
|
||||
// for the switch statement if the value being switched on exceeds the largest
|
||||
// case in the switch.
|
||||
SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
|
||||
TLI.getSetCCResultType(Sub.getValueType()), Sub,
|
||||
DAG.getConstant(JTH.Last-JTH.First,VT),
|
||||
TLI.getSetCCResultType(*DAG.getContext(),
|
||||
Sub.getValueType()),
|
||||
Sub,
|
||||
DAG.getConstant(JTH.Last - JTH.First,VT),
|
||||
ISD::SETUGT);
|
||||
|
||||
// Set NextBlock to be the MBB immediately after the current one, if any.
|
||||
@ -1745,7 +1747,8 @@ void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
|
||||
|
||||
// Check range
|
||||
SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
|
||||
TLI.getSetCCResultType(Sub.getValueType()),
|
||||
TLI.getSetCCResultType(*DAG.getContext(),
|
||||
Sub.getValueType()),
|
||||
Sub, DAG.getConstant(B.Range, VT),
|
||||
ISD::SETUGT);
|
||||
|
||||
@ -1811,14 +1814,14 @@ void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
|
||||
// Testing for a single bit; just compare the shift count with what it
|
||||
// would need to be to shift a 1 bit in that position.
|
||||
Cmp = DAG.getSetCC(getCurDebugLoc(),
|
||||
TLI.getSetCCResultType(VT),
|
||||
TLI.getSetCCResultType(*DAG.getContext(), VT),
|
||||
ShiftOp,
|
||||
DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
|
||||
ISD::SETEQ);
|
||||
} else if (PopCount == BB.Range) {
|
||||
// There is only one zero bit in the range, test for it directly.
|
||||
Cmp = DAG.getSetCC(getCurDebugLoc(),
|
||||
TLI.getSetCCResultType(VT),
|
||||
TLI.getSetCCResultType(*DAG.getContext(), VT),
|
||||
ShiftOp,
|
||||
DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
|
||||
ISD::SETNE);
|
||||
@ -1831,7 +1834,7 @@ void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
|
||||
SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
|
||||
VT, SwitchVal, DAG.getConstant(B.Mask, VT));
|
||||
Cmp = DAG.getSetCC(getCurDebugLoc(),
|
||||
TLI.getSetCCResultType(VT),
|
||||
TLI.getSetCCResultType(*DAG.getContext(), VT),
|
||||
AndOp, DAG.getConstant(0, VT),
|
||||
ISD::SETNE);
|
||||
}
|
||||
|
@ -187,10 +187,12 @@ void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
|
||||
NewRHS = DAG.getConstant(0, RetVT);
|
||||
CCCode = getCmpLibcallCC(LC1);
|
||||
if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
|
||||
SDValue Tmp = DAG.getNode(ISD::SETCC, dl, getSetCCResultType(RetVT),
|
||||
SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
|
||||
getSetCCResultType(*DAG.getContext(), RetVT),
|
||||
NewLHS, NewRHS, DAG.getCondCode(CCCode));
|
||||
NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/, dl);
|
||||
NewLHS = DAG.getNode(ISD::SETCC, dl, getSetCCResultType(RetVT), NewLHS,
|
||||
NewLHS = DAG.getNode(ISD::SETCC, dl,
|
||||
getSetCCResultType(*DAG.getContext(), RetVT), NewLHS,
|
||||
NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
|
||||
NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
|
||||
NewRHS = SDValue();
|
||||
|
@ -1033,7 +1033,7 @@ void TargetLoweringBase::computeRegisterProperties() {
|
||||
}
|
||||
}
|
||||
|
||||
EVT TargetLoweringBase::getSetCCResultType(EVT VT) const {
|
||||
EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const {
|
||||
assert(!VT.isVector() && "No default SetCC type for vectors!");
|
||||
return getPointerTy(0).SimpleTy;
|
||||
}
|
||||
|
@ -260,7 +260,7 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
|
||||
setExceptionSelectorRegister(AArch64::X1);
|
||||
}
|
||||
|
||||
EVT AArch64TargetLowering::getSetCCResultType(EVT VT) const {
|
||||
EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
|
||||
// It's reasonably important that this value matches the "natural" legal
|
||||
// promotion from i1 for scalar types. Otherwise LegalizeTypes can get itself
|
||||
// in a twist (e.g. inserting an any_extend which then becomes i64 -> i64).
|
||||
|
@ -171,7 +171,7 @@ public:
|
||||
SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
|
||||
MachineFrameInfo *MFI, int ClobberedFI) const;
|
||||
|
||||
EVT getSetCCResultType(EVT VT) const;
|
||||
EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
|
||||
|
||||
bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
|
||||
|
||||
|
@ -1069,7 +1069,7 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
|
||||
}
|
||||
}
|
||||
|
||||
EVT ARMTargetLowering::getSetCCResultType(EVT VT) const {
|
||||
EVT ARMTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
|
||||
if (!VT.isVector()) return getPointerTy();
|
||||
return VT.changeVectorElementTypeToInteger();
|
||||
}
|
||||
|
@ -270,7 +270,7 @@ namespace llvm {
|
||||
}
|
||||
|
||||
/// getSetCCResultType - Return the value type to use for ISD::SETCC.
|
||||
virtual EVT getSetCCResultType(EVT VT) const;
|
||||
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
|
||||
|
||||
virtual MachineBasicBlock *
|
||||
EmitInstrWithCustomInserter(MachineInstr *MI,
|
||||
|
@ -139,7 +139,7 @@ namespace llvm {
|
||||
|
||||
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
|
||||
virtual EVT getSetCCResultType(EVT VT) const {
|
||||
virtual EVT getSetCCResultType(LLVMContext &, EVT) const {
|
||||
return MVT::i1;
|
||||
}
|
||||
|
||||
|
@ -192,7 +192,7 @@ MBlazeTargetLowering::MBlazeTargetLowering(MBlazeTargetMachine &TM)
|
||||
computeRegisterProperties();
|
||||
}
|
||||
|
||||
EVT MBlazeTargetLowering::getSetCCResultType(EVT VT) const {
|
||||
EVT MBlazeTargetLowering::getSetCCResultType(LLVMContext &, EVT) const {
|
||||
return MVT::i32;
|
||||
}
|
||||
|
||||
|
@ -102,7 +102,7 @@ namespace llvm {
|
||||
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
||||
|
||||
/// getSetCCResultType - get the ISD::SETCC result ValueType
|
||||
EVT getSetCCResultType(EVT VT) const;
|
||||
EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
|
||||
|
||||
private:
|
||||
// Subtarget Info
|
||||
|
@ -409,7 +409,7 @@ const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) {
|
||||
return llvm::createMipsSETargetLowering(TM);
|
||||
}
|
||||
|
||||
EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
|
||||
EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
|
||||
if (!VT.isVector())
|
||||
return MVT::i32;
|
||||
return VT.changeVectorElementTypeToInteger();
|
||||
@ -1420,7 +1420,8 @@ lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
|
||||
{
|
||||
DebugLoc DL = Op.getDebugLoc();
|
||||
EVT Ty = Op.getOperand(0).getValueType();
|
||||
SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty),
|
||||
SDValue Cond = DAG.getNode(ISD::SETCC, DL,
|
||||
getSetCCResultType(*DAG.getContext(), Ty),
|
||||
Op.getOperand(0), Op.getOperand(1),
|
||||
Op.getOperand(4));
|
||||
|
||||
|
@ -195,7 +195,7 @@ namespace llvm {
|
||||
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
||||
|
||||
/// getSetCCResultType - get the ISD::SETCC result ValueType
|
||||
EVT getSetCCResultType(EVT VT) const;
|
||||
EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
|
||||
|
||||
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
||||
|
||||
|
@ -100,7 +100,7 @@ public:
|
||||
/// getFunctionAlignment - Return the Log2 alignment of this function.
|
||||
virtual unsigned getFunctionAlignment(const Function *F) const;
|
||||
|
||||
virtual EVT getSetCCResultType(EVT VT) const {
|
||||
virtual EVT getSetCCResultType(LLVMContext &, EVT VT) const {
|
||||
if (VT.isVector())
|
||||
return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
|
||||
return MVT::i1;
|
||||
|
@ -675,7 +675,7 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
|
||||
}
|
||||
}
|
||||
|
||||
EVT PPCTargetLowering::getSetCCResultType(EVT VT) const {
|
||||
EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
|
||||
if (!VT.isVector())
|
||||
return MVT::i32;
|
||||
return VT.changeVectorElementTypeToInteger();
|
||||
@ -2105,7 +2105,7 @@ PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
|
||||
else if (Flags.isZExt())
|
||||
ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
|
||||
DAG.getValueType(ObjectVT));
|
||||
|
||||
|
||||
return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
|
||||
}
|
||||
|
||||
@ -3868,7 +3868,7 @@ PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
|
||||
// register.
|
||||
// FIXME: The memcpy seems to produce pretty awful code for
|
||||
// small aggregates, particularly for packed ones.
|
||||
// FIXME: It would be preferable to use the slot in the
|
||||
// FIXME: It would be preferable to use the slot in the
|
||||
// parameter save area instead of a new local variable.
|
||||
SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
|
||||
SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
|
||||
@ -5724,7 +5724,7 @@ void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
|
||||
|
||||
assert(N->getValueType(0) == MVT::i1 &&
|
||||
"Unexpected result type for CTR decrement intrinsic");
|
||||
EVT SVT = getSetCCResultType(N->getValueType(0));
|
||||
EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
|
||||
SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
|
||||
SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
|
||||
N->getOperand(1));
|
||||
|
@ -226,7 +226,7 @@ namespace llvm {
|
||||
|
||||
/// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the
|
||||
/// local-dynamic TLS model, produces an ADDIS8 instruction
|
||||
/// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed
|
||||
/// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed
|
||||
/// to tie this in place following a copy to %X3 from the result
|
||||
/// of a GET_TLSLD_ADDR.
|
||||
ADDIS_DTPREL_HA,
|
||||
@ -348,7 +348,7 @@ namespace llvm {
|
||||
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
|
||||
|
||||
/// getSetCCResultType - Return the ISD::SETCC ValueType
|
||||
virtual EVT getSetCCResultType(EVT VT) const;
|
||||
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
|
||||
|
||||
/// getPreIndexedAddressParts - returns true by value, base pointer and
|
||||
/// offset pointer and addressing mode by reference if the node's address
|
||||
|
@ -1219,7 +1219,7 @@ SDValue R600TargetLowering::LowerFormalArguments(
|
||||
return Chain;
|
||||
}
|
||||
|
||||
EVT R600TargetLowering::getSetCCResultType(EVT VT) const {
|
||||
EVT R600TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
|
||||
if (!VT.isVector()) return MVT::i32;
|
||||
return VT.changeVectorElementTypeToInteger();
|
||||
}
|
||||
|
@ -38,7 +38,7 @@ public:
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
DebugLoc DL, SelectionDAG &DAG,
|
||||
SmallVectorImpl<SDValue> &InVals) const;
|
||||
virtual EVT getSetCCResultType(EVT VT) const;
|
||||
virtual EVT getSetCCResultType(LLVMContext &, EVT VT) const;
|
||||
private:
|
||||
const R600InstrInfo * TII;
|
||||
|
||||
|
@ -103,8 +103,8 @@ SDValue SITargetLowering::LowerFormalArguments(
|
||||
|
||||
for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
|
||||
const ISD::InputArg &Arg = Ins[i];
|
||||
|
||||
// First check if it's a PS input addr
|
||||
|
||||
// First check if it's a PS input addr
|
||||
if (Info->ShaderType == ShaderType::PIXEL && !Arg.Flags.isInReg()) {
|
||||
|
||||
assert((PSInputNum <= 15) && "Too many PS inputs!");
|
||||
@ -200,7 +200,7 @@ SDValue SITargetLowering::LowerFormalArguments(
|
||||
NumElements = Arg.VT.getVectorNumElements() - NumElements;
|
||||
for (unsigned j = 0; j != NumElements; ++j)
|
||||
Regs.push_back(DAG.getUNDEF(VT));
|
||||
|
||||
|
||||
InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT,
|
||||
Regs.data(), Regs.size()));
|
||||
continue;
|
||||
@ -222,7 +222,7 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
|
||||
return BB;
|
||||
}
|
||||
|
||||
EVT SITargetLowering::getSetCCResultType(EVT VT) const {
|
||||
EVT SITargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
|
||||
return MVT::i1;
|
||||
}
|
||||
|
||||
@ -433,13 +433,13 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
/// \brief Test if RegClass is one of the VSrc classes
|
||||
/// \brief Test if RegClass is one of the VSrc classes
|
||||
static bool isVSrc(unsigned RegClass) {
|
||||
return AMDGPU::VSrc_32RegClassID == RegClass ||
|
||||
AMDGPU::VSrc_64RegClassID == RegClass;
|
||||
}
|
||||
|
||||
/// \brief Test if RegClass is one of the SSrc classes
|
||||
/// \brief Test if RegClass is one of the SSrc classes
|
||||
static bool isSSrc(unsigned RegClass) {
|
||||
return AMDGPU::SSrc_32RegClassID == RegClass ||
|
||||
AMDGPU::SSrc_64RegClassID == RegClass;
|
||||
@ -516,7 +516,7 @@ bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
|
||||
bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, SDValue &Op,
|
||||
unsigned RegClass) const {
|
||||
|
||||
MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
|
||||
MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
|
||||
SDNode *Node = Op.getNode();
|
||||
|
||||
const TargetRegisterClass *OpClass;
|
||||
|
@ -31,7 +31,7 @@ class SITargetLowering : public AMDGPUTargetLowering {
|
||||
bool foldImm(SDValue &Operand, int32_t &Immediate,
|
||||
bool &ScalarSlotUsed) const;
|
||||
bool fitsRegClass(SelectionDAG &DAG, SDValue &Op, unsigned RegClass) const;
|
||||
void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
|
||||
void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
|
||||
unsigned RegClass, bool &ScalarSlotUsed) const;
|
||||
|
||||
SDNode *foldOperands(MachineSDNode *N, SelectionDAG &DAG) const;
|
||||
@ -48,7 +48,7 @@ public:
|
||||
|
||||
virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
|
||||
MachineBasicBlock * BB) const;
|
||||
virtual EVT getSetCCResultType(EVT VT) const;
|
||||
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
|
||||
virtual MVT getScalarShiftAmountTy(EVT VT) const;
|
||||
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
|
||||
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
||||
|
@ -117,7 +117,7 @@ public:
|
||||
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE {
|
||||
return MVT::i32;
|
||||
}
|
||||
virtual EVT getSetCCResultType(EVT VT) const {
|
||||
virtual EVT getSetCCResultType(LLVMContext &, EVT) const {
|
||||
return MVT::i32;
|
||||
}
|
||||
virtual bool isFMAFasterThanMulAndAdd(EVT) const LLVM_OVERRIDE {
|
||||
|
@ -1361,7 +1361,7 @@ void X86TargetLowering::resetOperationActions() {
|
||||
setPrefFunctionAlignment(4); // 2^4 bytes.
|
||||
}
|
||||
|
||||
EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
|
||||
EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
|
||||
if (!VT.isVector()) return MVT::i8;
|
||||
return VT.changeVectorElementTypeToInteger();
|
||||
}
|
||||
@ -6722,10 +6722,10 @@ X86TargetLowering::LowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const {
|
||||
// (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
|
||||
unsigned Ratio = V.getValueSizeInBits() / V1.getValueSizeInBits();
|
||||
EVT FullVT = V.getValueType();
|
||||
EVT SubVecVT = EVT::getVectorVT(*Context,
|
||||
EVT SubVecVT = EVT::getVectorVT(*Context,
|
||||
FullVT.getVectorElementType(),
|
||||
FullVT.getVectorNumElements()/Ratio);
|
||||
V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
|
||||
V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
|
||||
DAG.getIntPtrConstant(0));
|
||||
}
|
||||
V1 = DAG.getNode(ISD::BITCAST, DL, V1.getValueType(), V);
|
||||
@ -8250,7 +8250,8 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
|
||||
APInt FF(32, 0x5F800000ULL);
|
||||
|
||||
// Check whether the sign bit is set.
|
||||
SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
|
||||
SDValue SignSet = DAG.getSetCC(dl,
|
||||
getSetCCResultType(*DAG.getContext(), MVT::i64),
|
||||
Op.getOperand(0), DAG.getConstant(0, MVT::i64),
|
||||
ISD::SETLT);
|
||||
|
||||
@ -17412,7 +17413,7 @@ static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
|
||||
static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
|
||||
const X86Subtarget *Subtarget) {
|
||||
EVT VT = N->getValueType(0);
|
||||
if (!VT.isVector())
|
||||
@ -17432,14 +17433,14 @@ static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
|
||||
N0.getOpcode() == ISD::SIGN_EXTEND)) {
|
||||
SDValue N00 = N0.getOperand(0);
|
||||
|
||||
// EXTLOAD has a better solution on AVX2,
|
||||
// EXTLOAD has a better solution on AVX2,
|
||||
// it may be replaced with X86ISD::VSEXT node.
|
||||
if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
|
||||
if (!ISD::isNormalLoad(N00.getNode()))
|
||||
return SDValue();
|
||||
|
||||
if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
|
||||
SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
|
||||
SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
|
||||
N00, N1);
|
||||
return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
|
||||
}
|
||||
|
@ -511,7 +511,7 @@ namespace llvm {
|
||||
/// It returns EVT::Other if the type should be determined using generic
|
||||
/// target-independent logic.
|
||||
virtual EVT
|
||||
getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
|
||||
getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
|
||||
bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
|
||||
MachineFunction &MF) const;
|
||||
|
||||
@ -563,7 +563,7 @@ namespace llvm {
|
||||
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
||||
|
||||
/// getSetCCResultType - Return the value type to use for ISD::SETCC.
|
||||
virtual EVT getSetCCResultType(EVT VT) const;
|
||||
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
|
||||
|
||||
/// computeMaskedBitsForTargetNode - Determine which of the bits specified
|
||||
/// in Mask are known to be either zero or one and return them in the
|
||||
|
Loading…
Reference in New Issue
Block a user