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expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31014 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -75,6 +75,10 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SDIV, MVT::i32, Expand);
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setOperationAction(ISD::UDIV, MVT::i32, Expand);
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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setOperationAction(ISD::VASTART, MVT::Other, Custom);
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setOperationAction(ISD::VAEND, MVT::Other, Expand);
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29
test/CodeGen/ARM/div.ll
Normal file
29
test/CodeGen/ARM/div.ll
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@ -0,0 +1,29 @@
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; RUN: llvm-as < %s | llc -march=arm &&
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; RUN: llvm-as < %s | llc -march=arm | grep __divsi3 &&
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; RUN: llvm-as < %s | llc -march=arm | grep __udivsi3 &&
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; RUN: llvm-as < %s | llc -march=arm | grep __modsi3 &&
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; RUN: llvm-as < %s | llc -march=arm | grep __umodsi3
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int %f1(int %a, int %b) {
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entry:
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%tmp1 = div int %a, %b
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ret int %tmp1
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}
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uint %f2(uint %a, uint %b) {
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entry:
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%tmp1 = div uint %a, %b
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ret uint %tmp1
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}
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int %f3(int %a, int %b) {
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entry:
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%tmp1 = rem int %a, %b
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ret int %tmp1
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}
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uint %f4(uint %a, uint %b) {
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entry:
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%tmp1 = rem uint %a, %b
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ret uint %tmp1
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}
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