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X86-MPX: Implemented encoding for MPX instructions.

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Added encoding tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239403 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky 2015-06-09 13:02:10 +00:00
parent ff7ef6c5c9
commit 22debdcab6
7 changed files with 121 additions and 3 deletions
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3
lib/Target/X86/Disassembler/X86Disassembler.cpp
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@ -546,6 +546,8 @@ static void translateImmediate(MCInst &mcInst, uint64_t immediate,
case TYPE_XMM512:
mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4)));
return;
case TYPE_BNDR:
mcInst.addOperand(MCOperand::createReg(X86::BND0 + (immediate >> 4)));
case TYPE_REL8:
isBranch = true;
pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize;
@ -827,6 +829,7 @@ static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
case TYPE_VK16:
case TYPE_DEBUGREG:
case TYPE_CONTROLREG:
case TYPE_BNDR:
return translateRMRegister(mcInst, insn);
case TYPE_M:
case TYPE_M8:

1
lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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@ -460,6 +460,7 @@ enum OperandEncoding {
ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \
ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \
ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \
ENUM_ENTRY(TYPE_BNDR, "MPX bounds register") \
\
ENUM_ENTRY(TYPE_Mv, "Memory operand of operand size") \
ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \

3
lib/Target/X86/X86InstrInfo.td
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@ -2457,6 +2457,9 @@ include "X86InstrAVX512.td"
include "X86InstrMMX.td"
include "X86Instr3DNow.td"
// MPX instructions
include "X86InstrMPX.td"
include "X86InstrVMX.td"
include "X86InstrSVM.td"

70
lib/Target/X86/X86InstrMPX.td Normal file
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@ -0,0 +1,70 @@
//===-- X86InstrMPX.td - MPX Instruction Set ---------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the X86 MPX instruction set, defining the
// instructions, and properties of the instructions which are needed for code
// generation, machine code emission, and analysis.
//
//===----------------------------------------------------------------------===//
multiclass mpx_bound_make<bits<8> opc, string OpcodeStr> {
def 32rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins i32mem:$src),
OpcodeStr#" \t{$src, $dst|$dst, $src}", []>,
Requires<[HasMPX, Not64BitMode]>;
def 64rm: RI<opc, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
OpcodeStr#" \t{$src, $dst|$dst, $src}", []>,
Requires<[HasMPX, In64BitMode]>;
}
defm BNDMK : mpx_bound_make<0x1B, "bndmk">, XS;
multiclass mpx_bound_check<bits<8> opc, string OpcodeStr> {
def 32rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, i32mem:$src2),
OpcodeStr#" \t{$src2, $src1|$src1, $src2}", []>,
Requires<[HasMPX, Not64BitMode]>;
def 64rm: RI<opc, MRMSrcMem, (outs), (ins BNDR:$src1, i64mem:$src2),
OpcodeStr#" \t{$src2, $src1|$src1, $src2}", []>,
Requires<[HasMPX, In64BitMode]>;
def 32rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR32:$src2),
OpcodeStr#" \t{$src2, $src1|$src1, $src2}", []>,
Requires<[HasMPX, Not64BitMode]>;
def 64rr: RI<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR64:$src2),
OpcodeStr#" \t{$src2, $src1|$src1, $src2}", []>,
Requires<[HasMPX, In64BitMode]>;
}
defm BNDCL : mpx_bound_check<0x1A, "bndcl">, XS;
defm BNDCU : mpx_bound_check<0x1A, "bndcu">, XD;
defm BNDCN : mpx_bound_check<0x1B, "bndcn">, XD;
def BNDMOVRMrr : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src),
"bndmov \t{$src, $dst|$dst, $src}", []>, PD,
Requires<[HasMPX]>;
def BNDMOVRM32rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
"bndmov \t{$src, $dst|$dst, $src}", []>, PD,
Requires<[HasMPX, Not64BitMode]>;
def BNDMOVRM64rm : RI<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i128mem:$src),
"bndmov \t{$src, $dst|$dst, $src}", []>, PD,
Requires<[HasMPX, In64BitMode]>;
def BNDMOVMRrr : I<0x1B, MRMDestReg, (outs BNDR:$dst), (ins BNDR:$src),
"bndmov \t{$src, $dst|$dst, $src}", []>, PD,
Requires<[HasMPX]>;
def BNDMOVMR32mr : I<0x1B, MRMDestMem, (outs i64mem:$dst), (ins BNDR:$src),
"bndmov \t{$src, $dst|$dst, $src}", []>, PD,
Requires<[HasMPX, Not64BitMode]>;
def BNDMOVMR64mr : RI<0x1B, MRMDestMem, (outs i128mem:$dst), (ins BNDR:$src),
"bndmov \t{$src, $dst|$dst, $src}", []>, PD,
Requires<[HasMPX, In64BitMode]>;
def BNDSTXmr: I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src),
"bndstx \t{$src, $dst|$dst, $src}", []>, TB,
Requires<[HasMPX]>;
def BNDLDXrm: I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
"bndldx \t{$src, $dst|$dst, $src}", []>, TB,
Requires<[HasMPX]>;

6
lib/Target/X86/X86RegisterInfo.td
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@ -304,9 +304,9 @@ def RIZ : X86Reg<"riz", 4>;
// Bound registers, used in MPX instructions
def BND0 : X86Reg<"bnd0", 0>;
def BND1 : X86Reg<"bnd1", 0>;
def BND2 : X86Reg<"bnd2", 0>;
def BND3 : X86Reg<"bnd3", 0>;
def BND1 : X86Reg<"bnd1", 1>;
def BND2 : X86Reg<"bnd2", 2>;
def BND3 : X86Reg<"bnd3", 3>;
//===----------------------------------------------------------------------===//
// Register Class Definitions... now that we have all of the pieces, define the

38
test/MC/X86/mpx-encodings.s Normal file
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@ -0,0 +1,38 @@
// RUN: llvm-mc -triple x86_64-unknown-unknown -mcpu=knl --show-encoding %s | FileCheck %s
// CHECK: bndmk (%rax), %bnd0
// CHECK: encoding: [0xf3,0x48,0x0f,0x1b,0x00]
bndmk (%rax), %bnd0
// CHECK: bndmk 1024(%rax), %bnd1
// CHECK: encoding: [0xf3,0x48,0x0f,0x1b,0x88,0x00,0x04,0x00,0x00]
bndmk 1024(%rax), %bnd1
// CHECK: bndmov %bnd2, %bnd1
// CHECK: encoding: [0x66,0x0f,0x1b,0xd1]
bndmov %bnd2, %bnd1
// CHECK: bndmov %bnd1, 1024(%r9)
// CHECK: encoding: [0x66,0x49,0x0f,0x1b,0x89,0x00,0x04,0x00,0x00]
bndmov %bnd1, 1024(%r9)
// CHECK: bndstx %bnd1, 1024(%rax)
// CHECK: encoding: [0x0f,0x1b,0x88,0x00,0x04,0x00,0x00]
bndstx %bnd1, 1024(%rax)
// CHECK: bndldx 1024(%r8), %bnd1
// CHECK: encoding: [0x41,0x0f,0x1a,0x88,0x00,0x04,0x00,0x00]
bndldx 1024(%r8), %bnd1
// CHECK: bndcl 121(%r10), %bnd1
// CHECK: encoding: [0xf3,0x49,0x0f,0x1a,0x4a,0x79]
bndcl 121(%r10), %bnd1
// CHECK: bndcn 121(%rcx), %bnd3
// CHECK: encoding: [0xf2,0x48,0x0f,0x1b,0x59,0x79]
bndcn 121(%rcx), %bnd3
// CHECK: bndcu %rdx, %bnd3
// CHECK: encoding: [0xf2,0x48,0x0f,0x1a,0xda]
bndcu %rdx, %bnd3

3
utils/TableGen/X86RecognizableInstr.cpp
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@ -1033,6 +1033,7 @@ OperandType RecognizableInstr::typeFromString(const std::string &s,
TYPE("vy64mem", TYPE_M64)
TYPE("vy64xmem", TYPE_M64)
TYPE("vz64mem", TYPE_M64)
TYPE("BNDR", TYPE_BNDR)
errs() << "Unhandled type string " << s << "\n";
llvm_unreachable("Unhandled type string");
}
@ -1102,6 +1103,7 @@ RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
ENCODING("VK16", ENCODING_RM)
ENCODING("VK32", ENCODING_RM)
ENCODING("VK64", ENCODING_RM)
ENCODING("BNDR", ENCODING_RM)
errs() << "Unhandled R/M register encoding " << s << "\n";
llvm_unreachable("Unhandled R/M register encoding");
}
@ -1141,6 +1143,7 @@ RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
ENCODING("VK16WM", ENCODING_REG)
ENCODING("VK32WM", ENCODING_REG)
ENCODING("VK64WM", ENCODING_REG)
ENCODING("BNDR", ENCODING_REG)
errs() << "Unhandled reg/opcode register encoding " << s << "\n";
llvm_unreachable("Unhandled reg/opcode register encoding");
}