mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
SelectNodeTo() may return a SDOperand that is different from the input.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29726 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
4b790573f7
commit
23329f5e03
lib/Target
utils/TableGen
@ -197,10 +197,9 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
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case ISD::FrameIndex: {
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int FI = cast<FrameIndexSDNode>(N)->getIndex();
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Result = CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
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CurDAG->getTargetFrameIndex(FI, MVT::i32),
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getI64Imm(0));
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return NULL;
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return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
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CurDAG->getTargetFrameIndex(FI, MVT::i32),
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getI64Imm(0)).Val;
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}
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case AlphaISD::GlobalBaseReg:
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Result = getGlobalBaseReg();
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@ -228,8 +227,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
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Chain, Chain.getValue(1));
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Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
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SDOperand(CNode, 1));
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Result = CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
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return NULL;
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return CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain).Val;
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}
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case ISD::READCYCLECOUNTER: {
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@ -266,24 +264,21 @@ SDNode *AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
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SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
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SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
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getGlobalBaseReg());
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Result = CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
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CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
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return NULL;
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return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
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CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode()).Val;
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}
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case ISD::TargetConstantFP: {
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ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
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bool isDouble = N->getValueType(0) == MVT::f64;
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MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
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if (CN->isExactlyValue(+0.0)) {
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Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
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T, CurDAG->getRegister(Alpha::F31, T),
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CurDAG->getRegister(Alpha::F31, T));
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return NULL;
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return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
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T, CurDAG->getRegister(Alpha::F31, T),
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CurDAG->getRegister(Alpha::F31, T)).Val;
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} else if ( CN->isExactlyValue(-0.0)) {
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Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
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T, CurDAG->getRegister(Alpha::F31, T),
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CurDAG->getRegister(Alpha::F31, T));
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return NULL;
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return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
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T, CurDAG->getRegister(Alpha::F31, T),
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CurDAG->getRegister(Alpha::F31, T)).Val;
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} else {
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abort();
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}
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@ -398,25 +398,21 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
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SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
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if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0)) {
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Result = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
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return CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64).Val;
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} else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0)) {
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Result = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
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return CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64).Val;
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} else
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assert(0 && "Unexpected FP constant!");
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return Result.Val;
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}
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case ISD::FrameIndex: { // TODO: reduce creepyness
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int FI = cast<FrameIndexSDNode>(N)->getIndex();
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if (N->hasOneUse()) {
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Result = CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
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CurDAG->getTargetFrameIndex(FI, MVT::i64));
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return NULL;
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} else {
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Result = SDOperand(CurDAG->getTargetNode(IA64::MOV, MVT::i64,
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CurDAG->getTargetFrameIndex(FI, MVT::i64)), 0);
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return Result.Val;
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}
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if (N->hasOneUse())
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return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
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CurDAG->getTargetFrameIndex(FI, MVT::i64)).Val;
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else
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return SDOperand(CurDAG->getTargetNode(IA64::MOV, MVT::i64,
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CurDAG->getTargetFrameIndex(FI, MVT::i64)), 0).Val;
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}
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case ISD::ConstantPool: { // TODO: nuke the constant pool
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@ -467,11 +463,10 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
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case MVT::i1: { // this is a bool
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Opc = IA64::LD1; // first we load a byte, then compare for != 0
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if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
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Result = CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
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return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
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SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
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CurDAG->getRegister(IA64::r0, MVT::i64),
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Chain).getValue(Op.ResNo);
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return NULL;
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CurDAG->getRegister(IA64::r0, MVT::i64),
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Chain).getValue(Op.ResNo).Val;
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}
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/* otherwise, we want to load a bool into something bigger: LD1
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will do that for us, so we just fall through */
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@ -486,9 +481,8 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
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}
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// TODO: comment this
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Result = CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
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Address, Chain).getValue(Op.ResNo);
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return NULL;
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return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
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Address, Chain).getValue(Op.ResNo).Val;
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}
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case ISD::TRUNCSTORE:
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@ -512,8 +506,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
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Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
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CurDAG->getConstant(1, MVT::i64),
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Tmp), 0);
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Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
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return NULL;
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return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain).Val;
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}
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case MVT::i64: Opc = IA64::ST8; break;
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case MVT::f64: Opc = IA64::STF8; break;
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@ -531,8 +524,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
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SDOperand N1, N2;
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AddToQueue(N1, N->getOperand(1));
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AddToQueue(N2, N->getOperand(2));
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Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
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return NULL;
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return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain).Val;
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}
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case ISD::BRCOND: {
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@ -542,9 +534,8 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
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MachineBasicBlock *Dest =
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cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
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//FIXME - we do NOT need long branches all the time
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Result = CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
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CurDAG->getBasicBlock(Dest), Chain);
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return NULL;
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return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
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CurDAG->getBasicBlock(Dest), Chain).Val;
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}
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case ISD::CALLSEQ_START:
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@ -554,17 +545,15 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
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IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
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SDOperand N0;
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AddToQueue(N0, N->getOperand(0));
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Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
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return NULL;
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return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0).Val;
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}
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case ISD::BR:
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// FIXME: we don't need long branches all the time!
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SDOperand N0;
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AddToQueue(N0, N->getOperand(0));
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Result = CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
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N->getOperand(1), N0);
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return NULL;
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return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
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N->getOperand(1), N0).Val;
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}
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return SelectCode(Result, Op);
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@ -1093,8 +1093,8 @@ SDNode *SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
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// FIXME: Handle div by immediate.
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unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
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Result = CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
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return NULL;
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return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
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TopPart).Val;
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}
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case ISD::MULHU:
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case ISD::MULHS: {
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@ -1106,7 +1106,7 @@ SDNode *SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
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SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
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MulLHS, MulRHS);
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// The high part is in the Y register.
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Result = CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
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return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)).Val;
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return NULL;
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}
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}
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@ -703,8 +703,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
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if (C.Val) {
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if (N.Val->hasOneUse()) {
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Result = CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C);
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return NULL;
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return CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C).Val;
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} else {
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SDNode *ResNode = CurDAG->getTargetNode(X86::MOV32ri, MVT::i32, C);
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Result = SDOperand(ResNode, 0);
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@ -2794,8 +2794,6 @@ public:
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if (NodeHasInFlag || HasImpInputs)
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Code += ", InFlag";
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emitCode(Code + ");");
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if (isRoot)
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emitCode(" return NULL;");
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emitCode("} else {");
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emitDecl("ResNode", 1);
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Code = " ResNode = CurDAG->getTargetNode(Opc" + utostr(OpcNo);
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@ -2812,9 +2810,8 @@ public:
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Code += ", InFlag";
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emitCode(Code + ");");
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emitCode(" Result = SDOperand(ResNode, 0);");
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if (isRoot)
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emitCode(" return Result.Val;");
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emitCode("}");
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emitCode("return Result.Val;");
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}
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return std::make_pair(1, ResNo);
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