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Add instruction annotation about whether it has a 0x0F opcode prefix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4740 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -118,16 +118,16 @@ I(FNSTSWr8 , "fnstsw", 0, X86II::Void) // AX = fp flags DF E0
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// Condition code ops, incl. set if equal/not equal/...
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// Condition code ops, incl. set if equal/not equal/...
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I(SAHF , "sahf", 0, 0) // flags = AH 9E
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I(SAHF , "sahf", 0, 0) // flags = AH 9E
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I(SETA , "seta", 0, 0) // R8 = > unsign 0F 97
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I(SETA , "seta", 0, X86II::TB) // R8 = > unsign 0F 97
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I(SETAE , "setae", 0, 0) // R8 = >=unsign 0F 93
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I(SETAE , "setae", 0, X86II::TB) // R8 = >=unsign 0F 93
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I(SETB , "setb", 0, 0) // R8 = < unsign 0F 92
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I(SETB , "setb", 0, X86II::TB) // R8 = < unsign 0F 92
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I(SETBE , "setbe", 0, 0) // R8 = <=unsign 0F 96
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I(SETBE , "setbe", 0, X86II::TB) // R8 = <=unsign 0F 96
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I(SETE , "sete", 0, 0) // R8 = == 0F 94
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I(SETE , "sete", 0, X86II::TB) // R8 = == 0F 94
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I(SETG , "setg", 0, 0) // R8 = > signed 0F 9F
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I(SETG , "setg", 0, X86II::TB) // R8 = > signed 0F 9F
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I(SETGE , "setge", 0, 0) // R8 = >=signed 0F 9D
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I(SETGE , "setge", 0, X86II::TB) // R8 = >=signed 0F 9D
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I(SETL , "setl", 0, 0) // R8 = < signed 0F 9C
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I(SETL , "setl", 0, X86II::TB) // R8 = < signed 0F 9C
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I(SETLE , "setle", 0, 0) // R8 = <=signed 0F 9E
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I(SETLE , "setle", 0, X86II::TB) // R8 = <=signed 0F 9E
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I(SETNE , "setne", 0, 0) // R8 = != 0F 95
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I(SETNE , "setne", 0, X86II::TB) // R8 = != 0F 95
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// Integer comparisons
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// Integer comparisons
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I(CMPrr8 , "cmpb", 0, 0) // compare R8,R8 38/r
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I(CMPrr8 , "cmpb", 0, 0) // compare R8,R8 38/r
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@ -138,12 +138,12 @@ I(CMPrr32 , "cmpl", 0, 0) // compare R32,R32 39/r
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I(CBW , "cbw", 0, 0) // AX = signext(AL) 98
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I(CBW , "cbw", 0, 0) // AX = signext(AL) 98
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I(CWD , "cwd", 0, 0) // DX:AX = signext(AX) 99
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I(CWD , "cwd", 0, 0) // DX:AX = signext(AX) 99
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I(CDQ , "cdq", 0, 0) // EDX:EAX = signext(EAX) 99
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I(CDQ , "cdq", 0, 0) // EDX:EAX = signext(EAX) 99
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I(MOVSXr16r8 , "movsx", 0, 0) // R32 = signext(R8) 0F BE /r
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I(MOVSXr16r8 , "movsx", 0, X86II::TB) // R32 = signext(R8) 0F BE /r
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I(MOVSXr32r8 , "movsx", 0, 0) // R32 = signext(R8) 0F BE /r
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I(MOVSXr32r8 , "movsx", 0, X86II::TB) // R32 = signext(R8) 0F BE /r
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I(MOVSXr32r16 , "movsx", 0, 0) // R32 = signext(R16) 0F BF /r
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I(MOVSXr32r16 , "movsx", 0, X86II::TB) // R32 = signext(R16) 0F BF /r
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I(MOVZXr16r8 , "movzx", 0, 0) // R32 = zeroext(R8) 0F B6 /r
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I(MOVZXr16r8 , "movzx", 0, X86II::TB) // R32 = zeroext(R8) 0F B6 /r
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I(MOVZXr32r8 , "movzx", 0, 0) // R32 = zeroext(R8) 0F B6 /r
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I(MOVZXr32r8 , "movzx", 0, X86II::TB) // R32 = zeroext(R8) 0F B6 /r
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I(MOVZXr32r16 , "movzx", 0, 0) // R32 = zeroext(R16) 0F B7 /r
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I(MOVZXr32r16 , "movzx", 0, X86II::TB) // R32 = zeroext(R16) 0F B7 /r
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// At this point, I is dead, so undefine the macro
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// At this point, I is dead, so undefine the macro
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#undef I
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#undef I
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@ -15,7 +15,14 @@
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///
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///
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namespace X86II {
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namespace X86II {
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enum {
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enum {
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Void = 1 << 0, // Set if this instruction produces no value
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/// Void - Set if this instruction produces no value
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Void = 1 << 0,
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// TB - TwoByte - Set if this instruction has a two byte opcode, which
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// starts with a 0x0F byte before the real opcode.
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TB = 1 << 1,
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};
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};
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}
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}
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