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https://github.com/c64scene-ar/llvm-6502.git
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R600/SI: Combine min3/max3 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222032 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
a9d69424f4
commit
24e874a1dd
@ -2374,6 +2374,12 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
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NODE_NAME_CASE(FMIN_LEGACY)
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NODE_NAME_CASE(SMIN)
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NODE_NAME_CASE(UMIN)
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NODE_NAME_CASE(FMAX3)
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NODE_NAME_CASE(SMAX3)
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NODE_NAME_CASE(UMAX3)
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NODE_NAME_CASE(FMIN3)
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NODE_NAME_CASE(SMIN3)
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NODE_NAME_CASE(UMIN3)
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NODE_NAME_CASE(URECIP)
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NODE_NAME_CASE(DIV_SCALE)
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NODE_NAME_CASE(DIV_FMAS)
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@ -210,6 +210,12 @@ enum {
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FMIN_LEGACY,
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SMIN,
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UMIN,
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FMAX3,
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SMAX3,
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UMAX3,
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FMIN3,
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SMIN3,
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UMIN3,
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URECIP,
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DIV_SCALE,
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DIV_FMAS,
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@ -84,7 +84,7 @@ def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
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[SDNPAssociative]
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>;
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// out = min(a, b) a snd b are signed ints
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// out = min(a, b) a and b are signed ints
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def AMDGPUsmin : SDNode<"AMDGPUISD::SMIN", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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@ -94,6 +94,37 @@ def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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// FIXME: TableGen doesn't like commutative instructions with more
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// than 2 operands.
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// out = max(a, b, c) a, b and c are floats
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def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
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[/*SDNPCommutative, SDNPAssociative*/]
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>;
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// out = max(a, b, c) a, b, and c are signed ints
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def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
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[/*SDNPCommutative, SDNPAssociative*/]
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>;
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// out = max(a, b, c) a, b and c are unsigned ints
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def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,
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[/*SDNPCommutative, SDNPAssociative*/]
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>;
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// out = min(a, b, c) a, b and c are floats
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def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
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[/*SDNPCommutative, SDNPAssociative*/]
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>;
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// out = min(a, b, c) a, b and c are signed ints
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def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
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[/*SDNPCommutative, SDNPAssociative*/]
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>;
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// out = min(a, b) a and b are unsigned ints
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def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,
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[/*SDNPCommutative, SDNPAssociative*/]
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>;
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def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
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SDTIntToFPOp, []>;
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@ -231,6 +231,8 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
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setTargetDAGCombine(ISD::FADD);
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setTargetDAGCombine(ISD::FSUB);
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setTargetDAGCombine(ISD::FMINNUM);
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setTargetDAGCombine(ISD::FMAXNUM);
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setTargetDAGCombine(ISD::SELECT_CC);
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setTargetDAGCombine(ISD::SETCC);
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@ -1314,6 +1316,61 @@ SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
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return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset);
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}
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static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) {
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switch (Opc) {
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case ISD::FMAXNUM:
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return AMDGPUISD::FMAX3;
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case AMDGPUISD::SMAX:
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return AMDGPUISD::SMAX3;
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case AMDGPUISD::UMAX:
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return AMDGPUISD::UMAX3;
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case ISD::FMINNUM:
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return AMDGPUISD::FMIN3;
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case AMDGPUISD::SMIN:
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return AMDGPUISD::SMIN3;
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case AMDGPUISD::UMIN:
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return AMDGPUISD::UMIN3;
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default:
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llvm_unreachable("Not a min/max opcode");
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}
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}
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SDValue SITargetLowering::performMin3Max3Combine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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unsigned Opc = N->getOpcode();
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SDValue Op0 = N->getOperand(0);
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SDValue Op1 = N->getOperand(1);
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// Only do this if the inner op has one use since this will just increases
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// register pressure for no benefit.
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// max(max(a, b), c)
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if (Op0.getOpcode() == Opc && Op0.hasOneUse()) {
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SDLoc DL(N);
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return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
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DL,
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N->getValueType(0),
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Op0.getOperand(0),
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Op0.getOperand(1),
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Op1);
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}
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// max(a, max(b, c))
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if (Op1.getOpcode() == Opc && Op1.hasOneUse()) {
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SDLoc DL(N);
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return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
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DL,
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N->getValueType(0),
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Op0,
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Op1.getOperand(0),
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Op1.getOperand(1));
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}
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return SDValue();
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}
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SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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@ -1341,6 +1398,17 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
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}
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break;
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}
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case ISD::FMAXNUM: // TODO: What about fmax_legacy?
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case ISD::FMINNUM:
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case AMDGPUISD::SMAX:
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case AMDGPUISD::SMIN:
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case AMDGPUISD::UMAX:
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case AMDGPUISD::UMIN: {
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if (DCI.getDAGCombineLevel() >= AfterLegalizeDAG &&
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getTargetMachine().getOptLevel() > CodeGenOpt::None)
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return performMin3Max3Combine(N, DCI);
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break;
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}
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case AMDGPUISD::CVT_F32_UBYTE0:
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case AMDGPUISD::CVT_F32_UBYTE1:
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@ -59,6 +59,8 @@ class SITargetLowering : public AMDGPUTargetLowering {
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unsigned AS,
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DAGCombinerInfo &DCI) const;
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SDValue performMin3Max3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
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public:
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SITargetLowering(TargetMachine &tm);
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@ -1573,15 +1573,27 @@ defm V_ALIGNBYTE_B32 : VOP3Inst <vop3<0x14f>, "v_alignbyte_b32",
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>;
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defm V_MULLIT_F32 : VOP3Inst <vop3<0x150>, "v_mullit_f32",
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VOP_F32_F32_F32_F32>;
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////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "v_min3_f32", []>;
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////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "v_min3_i32", []>;
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////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "v_min3_u32", []>;
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////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "v_max3_f32", []>;
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////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "v_max3_i32", []>;
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////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "v_max3_u32", []>;
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////def V_MED3_F32 : VOP3_MED3 <0x00000157, "v_med3_f32", []>;
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////def V_MED3_I32 : VOP3_MED3 <0x00000158, "v_med3_i32", []>;
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////def V_MED3_U32 : VOP3_MED3 <0x00000159, "v_med3_u32", []>;
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defm V_MIN3_F32 : VOP3Inst <vop3<0x151>, "v_min3_f32",
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VOP_F32_F32_F32_F32, AMDGPUfmin3>;
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defm V_MIN3_I32 : VOP3Inst <vop3<0x152>, "v_min3_i32",
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VOP_I32_I32_I32_I32, AMDGPUsmin3
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>;
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defm V_MIN3_U32 : VOP3Inst <vop3<0x153>, "v_min3_u32",
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VOP_I32_I32_I32_I32, AMDGPUumin3
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>;
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defm V_MAX3_F32 : VOP3Inst <vop3<0x154>, "v_max3_f32",
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VOP_F32_F32_F32_F32, AMDGPUfmax3
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>;
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defm V_MAX3_I32 : VOP3Inst <vop3<0x155>, "v_max3_i32",
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VOP_I32_I32_I32_I32, AMDGPUsmax3
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>;
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defm V_MAX3_U32 : VOP3Inst <vop3<0x156>, "v_max3_u32",
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VOP_I32_I32_I32_I32, AMDGPUumax3
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>;
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//def V_MED3_F32 : VOP3_MED3 <0x00000157, "v_med3_f32", []>;
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//def V_MED3_I32 : VOP3_MED3 <0x00000158, "v_med3_i32", []>;
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//def V_MED3_U32 : VOP3_MED3 <0x00000159, "v_med3_u32", []>;
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//def V_SAD_U8 : VOP3_U8 <0x0000015a, "v_sad_u8", []>;
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//def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "v_sad_hi_u8", []>;
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//def V_SAD_U16 : VOP3_U16 <0x0000015c, "v_sad_u16", []>;
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38
test/CodeGen/R600/fmax3.ll
Normal file
38
test/CodeGen/R600/fmax3.ll
Normal file
@ -0,0 +1,38 @@
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare float @llvm.maxnum.f32(float, float) nounwind readnone
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; SI-LABEL: {{^}}test_fmax3_olt_0:
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; SI: buffer_load_dword [[REGA:v[0-9]+]]
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; SI: buffer_load_dword [[REGB:v[0-9]+]]
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; SI: buffer_load_dword [[REGC:v[0-9]+]]
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; SI: v_max3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
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; SI: buffer_store_dword [[RESULT]],
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; SI: s_endpgm
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define void @test_fmax3_olt_0(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind {
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%a = load float addrspace(1)* %aptr, align 4
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%b = load float addrspace(1)* %bptr, align 4
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%c = load float addrspace(1)* %cptr, align 4
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%f0 = call float @llvm.maxnum.f32(float %a, float %b) nounwind readnone
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%f1 = call float @llvm.maxnum.f32(float %f0, float %c) nounwind readnone
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store float %f1, float addrspace(1)* %out, align 4
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ret void
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}
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; Commute operand of second fmax
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; SI-LABEL: {{^}}test_fmax3_olt_1:
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; SI: buffer_load_dword [[REGA:v[0-9]+]]
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; SI: buffer_load_dword [[REGB:v[0-9]+]]
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; SI: buffer_load_dword [[REGC:v[0-9]+]]
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; SI: v_max3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
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; SI: buffer_store_dword [[RESULT]],
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; SI: s_endpgm
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define void @test_fmax3_olt_1(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind {
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%a = load float addrspace(1)* %aptr, align 4
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%b = load float addrspace(1)* %bptr, align 4
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%c = load float addrspace(1)* %cptr, align 4
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%f0 = call float @llvm.maxnum.f32(float %a, float %b) nounwind readnone
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%f1 = call float @llvm.maxnum.f32(float %c, float %f0) nounwind readnone
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store float %f1, float addrspace(1)* %out, align 4
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ret void
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}
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38
test/CodeGen/R600/fmin3.ll
Normal file
38
test/CodeGen/R600/fmin3.ll
Normal file
@ -0,0 +1,38 @@
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare float @llvm.minnum.f32(float, float) nounwind readnone
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; SI-LABEL: {{^}}test_fmin3_olt_0:
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; SI: buffer_load_dword [[REGA:v[0-9]+]]
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; SI: buffer_load_dword [[REGB:v[0-9]+]]
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; SI: buffer_load_dword [[REGC:v[0-9]+]]
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; SI: v_min3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
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; SI: buffer_store_dword [[RESULT]],
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; SI: s_endpgm
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define void @test_fmin3_olt_0(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind {
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%a = load float addrspace(1)* %aptr, align 4
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%b = load float addrspace(1)* %bptr, align 4
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%c = load float addrspace(1)* %cptr, align 4
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%f0 = call float @llvm.minnum.f32(float %a, float %b) nounwind readnone
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%f1 = call float @llvm.minnum.f32(float %f0, float %c) nounwind readnone
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store float %f1, float addrspace(1)* %out, align 4
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ret void
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}
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; Commute operand of second fmin
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; SI-LABEL: {{^}}test_fmin3_olt_1:
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; SI: buffer_load_dword [[REGA:v[0-9]+]]
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; SI: buffer_load_dword [[REGB:v[0-9]+]]
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; SI: buffer_load_dword [[REGC:v[0-9]+]]
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; SI: v_min3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]]
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; SI: buffer_store_dword [[RESULT]],
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; SI: s_endpgm
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define void @test_fmin3_olt_1(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind {
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%a = load float addrspace(1)* %aptr, align 4
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%b = load float addrspace(1)* %bptr, align 4
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%c = load float addrspace(1)* %cptr, align 4
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%f0 = call float @llvm.minnum.f32(float %a, float %b) nounwind readnone
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%f1 = call float @llvm.minnum.f32(float %c, float %f0) nounwind readnone
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store float %f1, float addrspace(1)* %out, align 4
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ret void
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}
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41
test/CodeGen/R600/max3.ll
Normal file
41
test/CodeGen/R600/max3.ll
Normal file
@ -0,0 +1,41 @@
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; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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; FUNC-LABEL: @v_test_imax3_sgt_i32
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; SI: v_max3_i32
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define void @v_test_imax3_sgt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr, i32 addrspace(1)* %cptr) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
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%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
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%gep2 = getelementptr i32 addrspace(1)* %cptr, i32 %tid
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%outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
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%a = load i32 addrspace(1)* %gep0, align 4
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%b = load i32 addrspace(1)* %gep1, align 4
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%c = load i32 addrspace(1)* %gep2, align 4
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%icmp0 = icmp sgt i32 %a, %b
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%i0 = select i1 %icmp0, i32 %a, i32 %b
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%icmp1 = icmp sgt i32 %i0, %c
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%i1 = select i1 %icmp1, i32 %i0, i32 %c
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store i32 %i1, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: @v_test_umax3_ugt_i32
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; SI: v_max3_u32
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define void @v_test_umax3_ugt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr, i32 addrspace(1)* %cptr) nounwind {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
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%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
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%gep2 = getelementptr i32 addrspace(1)* %cptr, i32 %tid
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%outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
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%a = load i32 addrspace(1)* %gep0, align 4
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%b = load i32 addrspace(1)* %gep1, align 4
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%c = load i32 addrspace(1)* %gep2, align 4
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%icmp0 = icmp ugt i32 %a, %b
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%i0 = select i1 %icmp0, i32 %a, i32 %b
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%icmp1 = icmp ugt i32 %i0, %c
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%i1 = select i1 %icmp1, i32 %i0, i32 %c
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store i32 %i1, i32 addrspace(1)* %out, align 4
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ret void
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}
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111
test/CodeGen/R600/min3.ll
Normal file
111
test/CodeGen/R600/min3.ll
Normal file
@ -0,0 +1,111 @@
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; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
|
||||
|
||||
; FUNC-LABEL: @v_test_imin3_slt_i32
|
||||
; SI: v_min3_i32
|
||||
define void @v_test_imin3_slt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr, i32 addrspace(1)* %cptr) nounwind {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
|
||||
%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
|
||||
%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
|
||||
%gep2 = getelementptr i32 addrspace(1)* %cptr, i32 %tid
|
||||
%outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
|
||||
%a = load i32 addrspace(1)* %gep0, align 4
|
||||
%b = load i32 addrspace(1)* %gep1, align 4
|
||||
%c = load i32 addrspace(1)* %gep2, align 4
|
||||
%icmp0 = icmp slt i32 %a, %b
|
||||
%i0 = select i1 %icmp0, i32 %a, i32 %b
|
||||
%icmp1 = icmp slt i32 %i0, %c
|
||||
%i1 = select i1 %icmp1, i32 %i0, i32 %c
|
||||
store i32 %i1, i32 addrspace(1)* %outgep, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @v_test_umin3_ult_i32
|
||||
; SI: v_min3_u32
|
||||
define void @v_test_umin3_ult_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr, i32 addrspace(1)* %cptr) nounwind {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
|
||||
%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
|
||||
%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
|
||||
%gep2 = getelementptr i32 addrspace(1)* %cptr, i32 %tid
|
||||
%outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
|
||||
%a = load i32 addrspace(1)* %gep0, align 4
|
||||
%b = load i32 addrspace(1)* %gep1, align 4
|
||||
%c = load i32 addrspace(1)* %gep2, align 4
|
||||
%icmp0 = icmp ult i32 %a, %b
|
||||
%i0 = select i1 %icmp0, i32 %a, i32 %b
|
||||
%icmp1 = icmp ult i32 %i0, %c
|
||||
%i1 = select i1 %icmp1, i32 %i0, i32 %c
|
||||
store i32 %i1, i32 addrspace(1)* %outgep, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @v_test_umin_umin_umin
|
||||
; SI: v_min_i32
|
||||
; SI: v_min3_i32
|
||||
define void @v_test_umin_umin_umin(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr, i32 addrspace(1)* %cptr) nounwind {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
|
||||
%tid2 = mul i32 %tid, 2
|
||||
%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
|
||||
%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
|
||||
%gep2 = getelementptr i32 addrspace(1)* %cptr, i32 %tid
|
||||
|
||||
%gep3 = getelementptr i32 addrspace(1)* %aptr, i32 %tid2
|
||||
%gep4 = getelementptr i32 addrspace(1)* %bptr, i32 %tid2
|
||||
%gep5 = getelementptr i32 addrspace(1)* %cptr, i32 %tid2
|
||||
|
||||
%outgep0 = getelementptr i32 addrspace(1)* %out, i32 %tid
|
||||
%outgep1 = getelementptr i32 addrspace(1)* %out, i32 %tid2
|
||||
|
||||
%a = load i32 addrspace(1)* %gep0, align 4
|
||||
%b = load i32 addrspace(1)* %gep1, align 4
|
||||
%c = load i32 addrspace(1)* %gep2, align 4
|
||||
%d = load i32 addrspace(1)* %gep3, align 4
|
||||
|
||||
%icmp0 = icmp slt i32 %a, %b
|
||||
%i0 = select i1 %icmp0, i32 %a, i32 %b
|
||||
|
||||
%icmp1 = icmp slt i32 %c, %d
|
||||
%i1 = select i1 %icmp1, i32 %c, i32 %d
|
||||
|
||||
%icmp2 = icmp slt i32 %i0, %i1
|
||||
%i2 = select i1 %icmp2, i32 %i0, i32 %i1
|
||||
|
||||
store i32 %i2, i32 addrspace(1)* %outgep1, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; FUNC-LABEL: @v_test_umin3_2_uses
|
||||
; SI-NOT: v_min3
|
||||
define void @v_test_umin3_2_uses(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr, i32 addrspace(1)* %cptr) nounwind {
|
||||
%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
|
||||
%tid2 = mul i32 %tid, 2
|
||||
%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
|
||||
%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
|
||||
%gep2 = getelementptr i32 addrspace(1)* %cptr, i32 %tid
|
||||
|
||||
%gep3 = getelementptr i32 addrspace(1)* %aptr, i32 %tid2
|
||||
%gep4 = getelementptr i32 addrspace(1)* %bptr, i32 %tid2
|
||||
%gep5 = getelementptr i32 addrspace(1)* %cptr, i32 %tid2
|
||||
|
||||
%outgep0 = getelementptr i32 addrspace(1)* %out, i32 %tid
|
||||
%outgep1 = getelementptr i32 addrspace(1)* %out, i32 %tid2
|
||||
|
||||
%a = load i32 addrspace(1)* %gep0, align 4
|
||||
%b = load i32 addrspace(1)* %gep1, align 4
|
||||
%c = load i32 addrspace(1)* %gep2, align 4
|
||||
%d = load i32 addrspace(1)* %gep3, align 4
|
||||
|
||||
%icmp0 = icmp slt i32 %a, %b
|
||||
%i0 = select i1 %icmp0, i32 %a, i32 %b
|
||||
|
||||
%icmp1 = icmp slt i32 %c, %d
|
||||
%i1 = select i1 %icmp1, i32 %c, i32 %d
|
||||
|
||||
%icmp2 = icmp slt i32 %i0, %c
|
||||
%i2 = select i1 %icmp2, i32 %i0, i32 %c
|
||||
|
||||
store i32 %i2, i32 addrspace(1)* %outgep0, align 4
|
||||
store i32 %i0, i32 addrspace(1)* %outgep1, align 4
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user