mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-12 13:30:51 +00:00
MC: Update MCCodeEmitter naming. NFC.
s/EncodeInstruction/encodeInstruction/ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237469 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
8b22e9c00a
commit
251a66ec37
@ -35,7 +35,7 @@ public:
|
||||
|
||||
/// EncodeInstruction - Encode the given \p Inst to bytes on the output
|
||||
/// stream \p OS.
|
||||
virtual void EncodeInstruction(const MCInst &Inst, raw_ostream &OS,
|
||||
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const = 0;
|
||||
};
|
||||
|
@ -1167,7 +1167,7 @@ void MCAsmStreamer::AddEncodingComment(const MCInst &Inst,
|
||||
SmallString<256> Code;
|
||||
SmallVector<MCFixup, 4> Fixups;
|
||||
raw_svector_ostream VecOS(Code);
|
||||
Emitter->EncodeInstruction(Inst, VecOS, Fixups, STI);
|
||||
Emitter->encodeInstruction(Inst, VecOS, Fixups, STI);
|
||||
VecOS.flush();
|
||||
|
||||
// If we are showing fixups, create symbolic markers in the encoded
|
||||
|
@ -1020,7 +1020,7 @@ bool MCAssembler::relaxInstruction(MCAsmLayout &Layout,
|
||||
SmallVector<MCFixup, 4> Fixups;
|
||||
SmallString<256> Code;
|
||||
raw_svector_ostream VecOS(Code);
|
||||
getEmitter().EncodeInstruction(Relaxed, VecOS, Fixups, F.getSubtargetInfo());
|
||||
getEmitter().encodeInstruction(Relaxed, VecOS, Fixups, F.getSubtargetInfo());
|
||||
VecOS.flush();
|
||||
|
||||
// Update the fragment.
|
||||
|
@ -479,7 +479,7 @@ void MCELFStreamer::EmitInstToData(const MCInst &Inst,
|
||||
SmallVector<MCFixup, 4> Fixups;
|
||||
SmallString<256> Code;
|
||||
raw_svector_ostream VecOS(Code);
|
||||
Assembler.getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
|
||||
Assembler.getEmitter().encodeInstruction(Inst, VecOS, Fixups, STI);
|
||||
VecOS.flush();
|
||||
|
||||
for (unsigned i = 0, e = Fixups.size(); i != e; ++i)
|
||||
|
@ -445,7 +445,7 @@ void MCMachOStreamer::EmitInstToData(const MCInst &Inst,
|
||||
SmallVector<MCFixup, 4> Fixups;
|
||||
SmallString<256> Code;
|
||||
raw_svector_ostream VecOS(Code);
|
||||
getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
|
||||
getAssembler().getEmitter().encodeInstruction(Inst, VecOS, Fixups, STI);
|
||||
VecOS.flush();
|
||||
|
||||
// Add the fixups and data.
|
||||
|
@ -256,7 +256,7 @@ void MCObjectStreamer::EmitInstToFragment(const MCInst &Inst,
|
||||
|
||||
SmallString<128> Code;
|
||||
raw_svector_ostream VecOS(Code);
|
||||
getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, IF->getFixups(),
|
||||
getAssembler().getEmitter().encodeInstruction(Inst, VecOS, IF->getFixups(),
|
||||
STI);
|
||||
VecOS.flush();
|
||||
IF->getContents().append(Code.begin(), Code.end());
|
||||
|
@ -49,7 +49,7 @@ void MCWinCOFFStreamer::EmitInstToData(const MCInst &Inst,
|
||||
SmallVector<MCFixup, 4> Fixups;
|
||||
SmallString<256> Code;
|
||||
raw_svector_ostream VecOS(Code);
|
||||
getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups, STI);
|
||||
getAssembler().getEmitter().encodeInstruction(Inst, VecOS, Fixups, STI);
|
||||
VecOS.flush();
|
||||
|
||||
// Add the fixups and data.
|
||||
|
@ -184,7 +184,7 @@ public:
|
||||
}
|
||||
}
|
||||
|
||||
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
void encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const override;
|
||||
|
||||
@ -598,7 +598,7 @@ unsigned AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue,
|
||||
return EncodedValue & ~(1u << 30);
|
||||
}
|
||||
|
||||
void AArch64MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
void AArch64MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const {
|
||||
if (MI.getOpcode() == AArch64::TLSDESCCALL) {
|
||||
|
@ -432,7 +432,7 @@ public:
|
||||
}
|
||||
}
|
||||
|
||||
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
void encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const override;
|
||||
};
|
||||
@ -1666,7 +1666,7 @@ getShiftRight64Imm(const MCInst &MI, unsigned Op,
|
||||
}
|
||||
|
||||
void ARMMCCodeEmitter::
|
||||
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const {
|
||||
// Pseudo instructions don't get encoded.
|
||||
|
@ -52,7 +52,7 @@ public:
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const;
|
||||
|
||||
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
void encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const override;
|
||||
};
|
||||
@ -117,7 +117,7 @@ void EmitBEConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
|
||||
EmitByte((Val >> i) & 255, CurByte, OS);
|
||||
}
|
||||
|
||||
void BPFMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
void BPFMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const {
|
||||
unsigned Opcode = MI.getOpcode();
|
||||
|
@ -55,7 +55,7 @@ HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII,
|
||||
: MCT(aMCT), MCII(aMII), Addend(new unsigned(0)),
|
||||
Extended(new bool(false)) {}
|
||||
|
||||
void HexagonMCCodeEmitter::EncodeInstruction(MCInst const &MI, raw_ostream &OS,
|
||||
void HexagonMCCodeEmitter::encodeInstruction(MCInst const &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
MCSubtargetInfo const &STI) const {
|
||||
uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI) | getPacketBits(MI);
|
||||
|
@ -41,7 +41,7 @@ public:
|
||||
|
||||
MCSubtargetInfo const &getSubtargetInfo() const;
|
||||
|
||||
void EncodeInstruction(MCInst const &MI, raw_ostream &OS,
|
||||
void encodeInstruction(MCInst const &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
MCSubtargetInfo const &STI) const override;
|
||||
|
||||
|
@ -141,10 +141,10 @@ void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size,
|
||||
}
|
||||
}
|
||||
|
||||
/// EncodeInstruction - Emit the instruction.
|
||||
/// encodeInstruction - Emit the instruction.
|
||||
/// Size the instruction with Desc.getSize().
|
||||
void MipsMCCodeEmitter::
|
||||
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const
|
||||
{
|
||||
@ -177,7 +177,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
unsigned Opcode = TmpInst.getOpcode();
|
||||
if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
|
||||
(Opcode != Mips::SLL_MM) && !Binary)
|
||||
llvm_unreachable("unimplemented opcode in EncodeInstruction()");
|
||||
llvm_unreachable("unimplemented opcode in encodeInstruction()");
|
||||
|
||||
int NewOpcode = -1;
|
||||
if (isMicroMips(STI)) {
|
||||
|
@ -51,7 +51,7 @@ public:
|
||||
void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI,
|
||||
raw_ostream &OS) const;
|
||||
|
||||
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
void encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const override;
|
||||
|
||||
|
@ -97,7 +97,7 @@ public:
|
||||
uint64_t getBinaryCodeForInstr(const MCInst &MI,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const;
|
||||
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
void encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const override {
|
||||
// For fast-isel, a float COPY_TO_REGCLASS can survive this long.
|
||||
|
@ -134,7 +134,7 @@ void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
||||
|
||||
auto &ObjStreamer = static_cast<MCObjectStreamer&>(*OutStreamer);
|
||||
MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter();
|
||||
InstEmitter.EncodeInstruction(TmpInst, CodeStream, Fixups,
|
||||
InstEmitter.encodeInstruction(TmpInst, CodeStream, Fixups,
|
||||
MF->getSubtarget<MCSubtargetInfo>());
|
||||
CodeStream.flush();
|
||||
|
||||
|
@ -41,7 +41,7 @@ public:
|
||||
: MCII(mcii), MRI(mri) { }
|
||||
|
||||
/// \brief Encode the instruction and write it to the OS.
|
||||
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
void encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const override;
|
||||
|
||||
@ -86,7 +86,7 @@ MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
|
||||
return new R600MCCodeEmitter(MCII, MRI);
|
||||
}
|
||||
|
||||
void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
void R600MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const {
|
||||
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
|
||||
|
@ -52,7 +52,7 @@ public:
|
||||
~SIMCCodeEmitter() override {}
|
||||
|
||||
/// \brief Encode the instruction and write it to the OS.
|
||||
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
void encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const override;
|
||||
|
||||
@ -179,7 +179,7 @@ uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
|
||||
return getLit64Encoding(static_cast<uint64_t>(MO.getImm()));
|
||||
}
|
||||
|
||||
void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const {
|
||||
|
||||
|
@ -41,7 +41,7 @@ public:
|
||||
|
||||
~SparcMCCodeEmitter() override {}
|
||||
|
||||
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
void encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const override;
|
||||
|
||||
@ -79,7 +79,7 @@ MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII,
|
||||
return new SparcMCCodeEmitter(Ctx);
|
||||
}
|
||||
|
||||
void SparcMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const {
|
||||
unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
|
||||
@ -154,7 +154,7 @@ getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
|
||||
|
||||
if (MI.getOpcode() == SP::TLS_CALL) {
|
||||
// No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in
|
||||
// EncodeInstruction.
|
||||
// encodeInstruction.
|
||||
#ifndef NDEBUG
|
||||
// Verify that the callee is actually __tls_get_addr.
|
||||
const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr());
|
||||
|
@ -35,7 +35,7 @@ public:
|
||||
~SystemZMCCodeEmitter() override {}
|
||||
|
||||
// OVerride MCCodeEmitter.
|
||||
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
void encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const override;
|
||||
|
||||
@ -118,7 +118,7 @@ MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
|
||||
}
|
||||
|
||||
void SystemZMCCodeEmitter::
|
||||
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const {
|
||||
uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
|
||||
|
@ -149,7 +149,7 @@ public:
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const;
|
||||
|
||||
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
void encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const override;
|
||||
|
||||
@ -1152,7 +1152,7 @@ void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
|
||||
}
|
||||
|
||||
void X86MCCodeEmitter::
|
||||
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
encodeInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI) const {
|
||||
unsigned Opcode = MI.getOpcode();
|
||||
|
@ -87,7 +87,7 @@ namespace llvm {
|
||||
SmallString<256> Code;
|
||||
SmallVector<MCFixup, 4> Fixups;
|
||||
raw_svector_ostream VecOS(Code);
|
||||
CodeEmitter->EncodeInstruction(Inst, VecOS, Fixups, STI);
|
||||
CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
|
||||
VecOS.flush();
|
||||
CurrentShadowSize += Code.size();
|
||||
if (CurrentShadowSize >= RequiredShadowSize)
|
||||
|
Loading…
Reference in New Issue
Block a user