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The machine instruction no longer encodes the submode as a separate operand. We

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should get the submode from the load/store multiple instruction's opcode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119461 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2010-11-17 05:31:09 +00:00
parent 0f63075613
commit 2567eec423
3 changed files with 14 additions and 6 deletions
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2
lib/Target/ARM/ARMAddressingModes.h
View File

@ -576,6 +576,8 @@ namespace ARM_AM {
return Val;
}
AMSubMode getLoadStoreMultipleSubMode(int Opcode);
} // end namespace ARM_AM
} // end namespace llvm

8
lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -1190,8 +1190,8 @@ void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
// Set addressing mode by modifying bits U(23) and P(24)
const MachineOperand &MO = MI.getOperand(OpIdx++);
Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
// Set bit W(21)
if (IsUpdating)
@ -1638,8 +1638,8 @@ ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
// Set addressing mode by modifying bits U(23) and P(24)
const MachineOperand &MO = MI.getOperand(OpIdx++);
Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
// Set bit W(21)
if (IsUpdating)

10
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -206,7 +206,10 @@ static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
return 0;
}
static ARM_AM::AMSubMode getLoadStoreMultipleSubMode(int Opcode) {
namespace llvm {
namespace ARM_AM {
AMSubMode getLoadStoreMultipleSubMode(int Opcode) {
switch (Opcode) {
default: llvm_unreachable("Unhandled opcode!");
case ARM::LDMIA:
@ -241,6 +244,9 @@ static ARM_AM::AMSubMode getLoadStoreMultipleSubMode(int Opcode) {
return ARM_AM::bad_am_submode;
}
} // end namespace ARM_AM
} // end namespace llvm
static bool isT2i32Load(unsigned Opc) {
return Opc == ARM::t2LDRi12 || Opc == ARM::t2LDRi8;
}
@ -670,7 +676,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
return false;
bool DoMerge = false;
ARM_AM::AMSubMode Mode = getLoadStoreMultipleSubMode(Opcode);
ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(Opcode);
// Try merging with the previous instruction.
MachineBasicBlock::iterator BeginMBBI = MBB.begin();