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The machine instruction no longer encodes the submode as a separate operand. We
should get the submode from the load/store multiple instruction's opcode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119461 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -576,6 +576,8 @@ namespace ARM_AM {
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return Val;
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}
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AMSubMode getLoadStoreMultipleSubMode(int Opcode);
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} // end namespace ARM_AM
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} // end namespace llvm
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@ -1190,8 +1190,8 @@ void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
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Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
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// Set addressing mode by modifying bits U(23) and P(24)
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const MachineOperand &MO = MI.getOperand(OpIdx++);
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Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
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ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
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Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
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// Set bit W(21)
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if (IsUpdating)
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@ -1638,8 +1638,8 @@ ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
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Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
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// Set addressing mode by modifying bits U(23) and P(24)
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const MachineOperand &MO = MI.getOperand(OpIdx++);
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Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
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ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
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Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
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// Set bit W(21)
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if (IsUpdating)
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@ -206,7 +206,10 @@ static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
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return 0;
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}
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static ARM_AM::AMSubMode getLoadStoreMultipleSubMode(int Opcode) {
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namespace llvm {
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namespace ARM_AM {
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AMSubMode getLoadStoreMultipleSubMode(int Opcode) {
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switch (Opcode) {
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default: llvm_unreachable("Unhandled opcode!");
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case ARM::LDMIA:
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@ -241,6 +244,9 @@ static ARM_AM::AMSubMode getLoadStoreMultipleSubMode(int Opcode) {
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return ARM_AM::bad_am_submode;
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}
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} // end namespace ARM_AM
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} // end namespace llvm
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static bool isT2i32Load(unsigned Opc) {
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return Opc == ARM::t2LDRi12 || Opc == ARM::t2LDRi8;
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}
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@ -670,7 +676,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
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return false;
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bool DoMerge = false;
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ARM_AM::AMSubMode Mode = getLoadStoreMultipleSubMode(Opcode);
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ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(Opcode);
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// Try merging with the previous instruction.
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MachineBasicBlock::iterator BeginMBBI = MBB.begin();
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