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https://github.com/c64scene-ar/llvm-6502.git
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Remove some unnecessary forward declarations and put a couple more
where they're supposed to reside. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232014 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -21,10 +21,6 @@
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#include "ARMGenRegisterInfo.inc"
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namespace llvm {
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class ARMSubtarget;
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class ARMBaseInstrInfo;
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class Type;
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/// Register allocation hints.
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namespace ARMRI {
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enum {
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@ -26,7 +26,7 @@
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namespace llvm {
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struct EVT;
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class HexagonSubtarget;
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class HexagonInstrInfo : public HexagonGenInstrInfo {
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virtual void anchor();
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const HexagonRegisterInfo RI;
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@ -37,11 +37,6 @@
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#define HEXAGON_RESERVED_REG_2 Hexagon::R11
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namespace llvm {
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class HexagonSubtarget;
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class HexagonInstrInfo;
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class Type;
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struct HexagonRegisterInfo : public HexagonGenRegisterInfo {
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HexagonRegisterInfo();
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@ -21,8 +21,6 @@
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#include "MipsGenRegisterInfo.inc"
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namespace llvm {
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class Type;
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class MipsRegisterInfo : public MipsGenRegisterInfo {
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public:
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MipsRegisterInfo();
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@ -63,7 +63,7 @@ enum PPC970_Unit {
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};
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} // end namespace PPCII
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class PPCSubtarget;
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class PPCInstrInfo : public PPCGenInstrInfo {
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PPCSubtarget &Subtarget;
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const PPCRegisterInfo RI;
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@ -22,10 +22,6 @@
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#include "PPCGenRegisterInfo.inc"
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namespace llvm {
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class PPCSubtarget;
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class TargetInstrInfo;
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class Type;
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class PPCRegisterInfo : public PPCGenRegisterInfo {
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DenseMap<unsigned, unsigned> ImmToIdxMap;
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const PPCTargetMachine &TM;
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@ -20,10 +20,6 @@
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#include "SparcGenRegisterInfo.inc"
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namespace llvm {
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class TargetInstrInfo;
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class Type;
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struct SparcRegisterInfo : public SparcGenRegisterInfo {
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SparcRegisterInfo();
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@ -20,9 +20,7 @@
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#include "X86GenRegisterInfo.inc"
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namespace llvm {
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class Type;
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class TargetInstrInfo;
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class X86Subtarget;
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class X86Subtarget;
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class X86RegisterInfo final : public X86GenRegisterInfo {
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public:
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