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Enhance boolean simplification to handle 16-/64-bit RDRAND

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- RDRAND always clears the destination value when a random value is not
  available (i.e. CF == 0). This value is truncated or zero-extended as
  the false boolean value to be returned. Boolean simplification needs
  to skip this 'zext' or 'trunc' node.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178312 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michael Liao 2013-03-28 23:38:52 +00:00
parent 816f6d0ac7
commit 258d9b7bc0
2 changed files with 43 additions and 6 deletions
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13
lib/Target/X86/X86ISelLowering.cpp
View File

@ -15821,8 +15821,9 @@ static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
// Quit if the constant is neither 0 or 1.
return SDValue();
// Skip 'zext' node.
if (SetCC.getOpcode() == ISD::ZERO_EXTEND)
// Skip 'zext' or 'trunc' node.
if (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
SetCC.getOpcode() == ISD::TRUNCATE)
SetCC = SetCC.getOperand(0);
switch (SetCC.getOpcode()) {
@ -15841,9 +15842,13 @@ static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
return SDValue();
// Quit if false value is not a constant.
if (!FVal) {
// A special case for rdrand, where 0 is set if false cond is found.
SDValue Op = SetCC.getOperand(0);
if (Op.getOpcode() != X86ISD::RDRAND)
// Skip 'zext' or 'trunc' node.
if (Op.getOpcode() == ISD::ZERO_EXTEND ||
Op.getOpcode() == ISD::TRUNCATE)
Op = Op.getOperand(0);
// A special case for rdrand, where 0 is set if false cond is found.
if (Op.getOpcode() != X86ISD::RDRAND || Op.getResNo() != 0)
return SDValue();
}
// Quit if false value is not the constant 0 or 1.

36
test/CodeGen/X86/bool-simplify.ll
View File

@ -39,7 +39,22 @@ define i32 @bax(<2 x i64> %c) {
; CHECK: ret
}
define i32 @rnd(i32 %arg) nounwind uwtable {
define i16 @rnd16(i16 %arg) nounwind uwtable {
%1 = tail call { i16, i32 } @llvm.x86.rdrand.16() nounwind
%2 = extractvalue { i16, i32 } %1, 0
%3 = extractvalue { i16, i32 } %1, 1
%4 = icmp eq i32 %3, 0
%5 = select i1 %4, i16 0, i16 %arg
%6 = add i16 %5, %2
ret i16 %6
; CHECK: rnd16
; CHECK: rdrand
; CHECK: cmov
; CHECK-NOT: cmov
; CHECK: ret
}
define i32 @rnd32(i32 %arg) nounwind uwtable {
%1 = tail call { i32, i32 } @llvm.x86.rdrand.32() nounwind
%2 = extractvalue { i32, i32 } %1, 0
%3 = extractvalue { i32, i32 } %1, 1
@ -47,7 +62,22 @@ define i32 @rnd(i32 %arg) nounwind uwtable {
%5 = select i1 %4, i32 0, i32 %arg
%6 = add i32 %5, %2
ret i32 %6
; CHECK: rnd
; CHECK: rnd32
; CHECK: rdrand
; CHECK: cmov
; CHECK-NOT: cmov
; CHECK: ret
}
define i64 @rnd64(i64 %arg) nounwind uwtable {
%1 = tail call { i64, i32 } @llvm.x86.rdrand.64() nounwind
%2 = extractvalue { i64, i32 } %1, 0
%3 = extractvalue { i64, i32 } %1, 1
%4 = icmp eq i32 %3, 0
%5 = select i1 %4, i64 0, i64 %arg
%6 = add i64 %5, %2
ret i64 %6
; CHECK: rnd64
; CHECK: rdrand
; CHECK: cmov
; CHECK-NOT: cmov
@ -55,4 +85,6 @@ define i32 @rnd(i32 %arg) nounwind uwtable {
}
declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone
declare { i16, i32 } @llvm.x86.rdrand.16() nounwind
declare { i32, i32 } @llvm.x86.rdrand.32() nounwind
declare { i64, i32 } @llvm.x86.rdrand.64() nounwind