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Add 32 bit and reg-imm and disable invalid patterns for now

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75978 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2009-07-16 14:05:32 +00:00
parent 747052c1a5
commit 25af73303f
8 changed files with 52 additions and 12 deletions
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29
lib/Target/SystemZ/SystemZInstrInfo.td
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@ -104,6 +104,17 @@ def HI32 : SDNodeXForm<imm, [{
return getI32Imm(N->getZExtValue() >> 32);
}]>;
def i32ll16 : PatLeaf<(i32 imm), [{
// i32ll16 predicate - true if the 32-bit immediate has only rightmost 16
// bits set.
return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue());
}], LL16>;
def i32lh16 : PatLeaf<(i32 imm), [{
// i32lh16 predicate - true if the 32-bit immediate has only bits 16-31 set.
return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue());
}], LH16>;
def i64ll16 : PatLeaf<(imm), [{
// i64ll16 predicate - true if the 64-bit immediate has only rightmost 16
// bits set.
@ -590,25 +601,39 @@ def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
}
// FIXME: Provide proper encoding!
// FIXME: Compute masked bits properly!
/*
def AND32rill16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
"nill\t{$dst, $src2}",
[(set GR32:$dst, (and GR32:$src1, i32ll16:$src2))]>;
def AND64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
"nill\t{$dst, $src2}",
[(set GR64:$dst, (and GR64:$src1, i64ll16:$src2))]>;
def AND32rilh16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
"nilh\t{$dst, $src2}",
[(set GR32:$dst, (and GR32:$src1, i32lh16:$src2))]>;
def AND64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
"nilh\t{$dst, $src2}",
[(set GR64:$dst, (and GR64:$src1, i64lh16:$src2))]>;
def AND64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
"nihl\t{$dst, $src2}",
[(set GR64:$dst, (and GR64:$src1, i64hl16:$src2))]>;
def AND64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
"nihh\t{$dst, $src2}",
[(set GR64:$dst, (and GR64:$src1, i64hh16:$src2))]>;
// FIXME: these 2 instructions seem to require extimm facility
def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
*/
def AND32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
"nilf\t{$dst, $src2}",
[(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
/*def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
"nilf\t{$dst, $src2}",
[(set GR64:$dst, (and GR64:$src1, i64lo32:$src2))]>;
def AND64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
"nihf\t{$dst, $src2}",
[(set GR64:$dst, (and GR64:$src1, i64hi32:$src2))]>;
*/
let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
// FIXME: Provide proper encoding!

1
test/CodeGen/SystemZ/02-RetAndImm.ll
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@ -1,3 +1,4 @@
; XFAIL: *
; RUN: llvm-as < %s | llc -march=systemz | grep nill | count 1
; RUN: llvm-as < %s | llc -march=systemz | grep nilh | count 1
; RUN: llvm-as < %s | llc -march=systemz | grep nihl | count 1

1
test/CodeGen/SystemZ/03-RetAndImmSubreg.ll
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@ -1,3 +1,4 @@
; XFAIL: *
; RUN: llvm-as < %s | llc -march=systemz | grep nill | count 3
; RUN: llvm-as < %s | llc -march=systemz | grep nilh | count 3

2
test/CodeGen/SystemZ/03-RetAndSubreg.ll
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@ -1,4 +1,4 @@
; RUN: llvm-as < %s | llc -march=systemz | grep ngr | count 3
; RUN: llvm-as < %s | llc -march=systemz | grep ngr | count 4
define i32 @foo(i32 %a, i32 %b) {
entry:

6
test/CodeGen/SystemZ/03-RetArgSubreg.ll
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@ -1,6 +1,6 @@
; RUN: llvm-as < %s | llc -march=systemz | grep lgr | count 2
; RUN: llvm-as < %s | llc -march=systemz | grep nilf | count 1
; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 1
; RUN: llvm-as < %s | llc -march=systemz | grep lgr | count 1
; RUN: llvm-as < %s | llc -march=systemz | grep llilf | count 1
; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 1
define i32 @foo(i32 %a, i32 %b) {

6
test/CodeGen/SystemZ/03-RetOrSubreg.ll
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@ -1,6 +1,6 @@
; RUN: llvm-as < %s | llc -march=systemz | grep ogr | count 3
; RUN: llvm-as < %s | llc -march=systemz | grep nilf | count 1
; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 1
; RUN: llvm-as < %s | llc -march=systemz | grep ogr | count 3
; RUN: llvm-as < %s | llc -march=systemz | grep llilf | count 1
; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 1
define i32 @foo(i32 %a, i32 %b) {

6
test/CodeGen/SystemZ/03-RetXorSubreg.ll
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@ -1,6 +1,6 @@
; RUN: llvm-as < %s | llc -march=systemz | grep xgr | count 3
; RUN: llvm-as < %s | llc -march=systemz | grep nilf | count 1
; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 1
; RUN: llvm-as < %s | llc -march=systemz | grep xgr | count 3
; RUN: llvm-as < %s | llc -march=systemz | grep llilf | count 1
; RUN: llvm-as < %s | llc -march=systemz | grep lgfr | count 1
define i32 @foo(i32 %a, i32 %b) {

13
test/CodeGen/SystemZ/2009-06-02-And32Imm.ll Normal file
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@ -0,0 +1,13 @@
; RUN: llvm-as < %s | llc -march=systemz | grep nilf | count 2
define i32 @gnu_dev_major(i64 %__dev) nounwind readnone {
entry:
%shr = lshr i64 %__dev, 8 ; <i64> [#uses=1]
%shr8 = trunc i64 %shr to i32 ; <i32> [#uses=1]
%shr2 = lshr i64 %__dev, 32 ; <i64> [#uses=1]
%conv = trunc i64 %shr2 to i32 ; <i32> [#uses=1]
%and3 = and i32 %conv, -4096 ; <i32> [#uses=1]
%and6 = and i32 %shr8, 4095 ; <i32> [#uses=1]
%conv5 = or i32 %and6, %and3 ; <i32> [#uses=1]
ret i32 %conv5
}