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Remove DwarfRegNum from the individual bits of the condition register.

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These should be DW_OP_bit_piece of CR (64).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132192 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2011-05-27 16:15:27 +00:00
parent 81a2745830
commit 25b15d8502
1 changed files with 32 additions and 32 deletions
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64
lib/Target/PowerPC/PPCRegisterInfo.td
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@ -201,38 +201,38 @@ def V30 : VR<30, "v30">, DwarfRegNum<[107]>;
def V31 : VR<31, "v31">, DwarfRegNum<[108]>;
// Condition register bits
def CR0LT : CRBIT< 0, "0">, DwarfRegNum<[0]>;
def CR0GT : CRBIT< 1, "1">, DwarfRegNum<[0]>;
def CR0EQ : CRBIT< 2, "2">, DwarfRegNum<[0]>;
def CR0UN : CRBIT< 3, "3">, DwarfRegNum<[0]>;
def CR1LT : CRBIT< 4, "4">, DwarfRegNum<[0]>;
def CR1GT : CRBIT< 5, "5">, DwarfRegNum<[0]>;
def CR1EQ : CRBIT< 6, "6">, DwarfRegNum<[0]>;
def CR1UN : CRBIT< 7, "7">, DwarfRegNum<[0]>;
def CR2LT : CRBIT< 8, "8">, DwarfRegNum<[0]>;
def CR2GT : CRBIT< 9, "9">, DwarfRegNum<[0]>;
def CR2EQ : CRBIT<10, "10">, DwarfRegNum<[0]>;
def CR2UN : CRBIT<11, "11">, DwarfRegNum<[0]>;
def CR3LT : CRBIT<12, "12">, DwarfRegNum<[0]>;
def CR3GT : CRBIT<13, "13">, DwarfRegNum<[0]>;
def CR3EQ : CRBIT<14, "14">, DwarfRegNum<[0]>;
def CR3UN : CRBIT<15, "15">, DwarfRegNum<[0]>;
def CR4LT : CRBIT<16, "16">, DwarfRegNum<[0]>;
def CR4GT : CRBIT<17, "17">, DwarfRegNum<[0]>;
def CR4EQ : CRBIT<18, "18">, DwarfRegNum<[0]>;
def CR4UN : CRBIT<19, "19">, DwarfRegNum<[0]>;
def CR5LT : CRBIT<20, "20">, DwarfRegNum<[0]>;
def CR5GT : CRBIT<21, "21">, DwarfRegNum<[0]>;
def CR5EQ : CRBIT<22, "22">, DwarfRegNum<[0]>;
def CR5UN : CRBIT<23, "23">, DwarfRegNum<[0]>;
def CR6LT : CRBIT<24, "24">, DwarfRegNum<[0]>;
def CR6GT : CRBIT<25, "25">, DwarfRegNum<[0]>;
def CR6EQ : CRBIT<26, "26">, DwarfRegNum<[0]>;
def CR6UN : CRBIT<27, "27">, DwarfRegNum<[0]>;
def CR7LT : CRBIT<28, "28">, DwarfRegNum<[0]>;
def CR7GT : CRBIT<29, "29">, DwarfRegNum<[0]>;
def CR7EQ : CRBIT<30, "30">, DwarfRegNum<[0]>;
def CR7UN : CRBIT<31, "31">, DwarfRegNum<[0]>;
def CR0LT : CRBIT< 0, "0">;
def CR0GT : CRBIT< 1, "1">;
def CR0EQ : CRBIT< 2, "2">;
def CR0UN : CRBIT< 3, "3">;
def CR1LT : CRBIT< 4, "4">;
def CR1GT : CRBIT< 5, "5">;
def CR1EQ : CRBIT< 6, "6">;
def CR1UN : CRBIT< 7, "7">;
def CR2LT : CRBIT< 8, "8">;
def CR2GT : CRBIT< 9, "9">;
def CR2EQ : CRBIT<10, "10">;
def CR2UN : CRBIT<11, "11">;
def CR3LT : CRBIT<12, "12">;
def CR3GT : CRBIT<13, "13">;
def CR3EQ : CRBIT<14, "14">;
def CR3UN : CRBIT<15, "15">;
def CR4LT : CRBIT<16, "16">;
def CR4GT : CRBIT<17, "17">;
def CR4EQ : CRBIT<18, "18">;
def CR4UN : CRBIT<19, "19">;
def CR5LT : CRBIT<20, "20">;
def CR5GT : CRBIT<21, "21">;
def CR5EQ : CRBIT<22, "22">;
def CR5UN : CRBIT<23, "23">;
def CR6LT : CRBIT<24, "24">;
def CR6GT : CRBIT<25, "25">;
def CR6EQ : CRBIT<26, "26">;
def CR6UN : CRBIT<27, "27">;
def CR7LT : CRBIT<28, "28">;
def CR7GT : CRBIT<29, "29">;
def CR7EQ : CRBIT<30, "30">;
def CR7UN : CRBIT<31, "31">;
// Condition registers
let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in {