mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-27 15:57:13 +00:00
Remove PreprocessCCCArguments and PreprocessFastCCArguments now that
FORMAL_ARGUMENTS nodes include a token operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28439 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
2d2970905c
commit
25caf63cd2
@ -358,22 +358,6 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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allowUnalignedMemoryAccesses = true; // x86 supports it!
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}
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std::vector<SDOperand>
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X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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std::vector<SDOperand> Args = TargetLowering::LowerArguments(F, DAG);
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FormalArgs.clear();
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FormalArgLocs.clear();
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// This sets BytesToPopOnReturn, BytesCallerReserves, etc. which have to be
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// set before the rest of the function can be lowered.
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if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
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PreprocessFastCCArguments(Args, F, DAG);
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else
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PreprocessCCCArguments(Args, F, DAG);
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return Args;
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}
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std::pair<SDOperand, SDOperand>
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X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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bool isVarArg, unsigned CallingConv,
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@ -463,11 +447,12 @@ static std::vector<SDOperand> getFormalArgObjects(SDOperand Op) {
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return Objs;
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}
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void X86TargetLowering::PreprocessCCCArguments(std::vector<SDOperand> &Args,
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Function &F, SelectionDAG &DAG) {
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unsigned NumArgs = Args.size();
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SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG) {
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unsigned NumArgs = Op.Val->getNumValues() - 1;
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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SDOperand Root = Op.getOperand(0);
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std::vector<SDOperand> ArgValues;
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// Add DAG nodes to load the arguments... On entry to a function on the X86,
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// the stack frame looks like this:
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@ -481,78 +466,53 @@ void X86TargetLowering::PreprocessCCCArguments(std::vector<SDOperand> &Args,
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unsigned NumXMMRegs = 0; // XMM regs used for parameter passing.
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unsigned XMMArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2 };
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for (unsigned i = 0; i < NumArgs; ++i) {
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SDOperand Op = Args[i];
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std::vector<SDOperand> Objs = getFormalArgObjects(Op);
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for (std::vector<SDOperand>::iterator I = Objs.begin(), E = Objs.end();
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I != E; ++I) {
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SDOperand Obj = *I;
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MVT::ValueType ObjectVT = Obj.getValueType();
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unsigned ArgIncrement = 4;
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unsigned ObjSize = 0;
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unsigned ObjXMMRegs = 0;
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HowToPassCCCArgument(ObjectVT, NumXMMRegs, ObjSize, ObjXMMRegs);
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if (ObjSize >= 8)
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ArgIncrement = ObjSize;
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MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
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unsigned ArgIncrement = 4;
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unsigned ObjSize = 0;
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unsigned ObjXMMRegs = 0;
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HowToPassCCCArgument(ObjectVT, NumXMMRegs, ObjSize, ObjXMMRegs);
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if (ObjSize >= 8)
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ArgIncrement = ObjSize;
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if (ObjXMMRegs) {
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// Passed in a XMM register.
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unsigned Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
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SDOperand ArgValue;
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if (ObjXMMRegs) {
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// Passed in a XMM register.
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unsigned Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
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X86::VR128RegisterClass);
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std::pair<FALocInfo, FALocInfo> Loc =
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std::make_pair(FALocInfo(FALocInfo::LiveInRegLoc, Reg, ObjectVT),
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FALocInfo());
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FormalArgLocs.push_back(Loc);
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NumXMMRegs += ObjXMMRegs;
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} else {
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// Create the frame index object for this incoming parameter...
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int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
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std::pair<FALocInfo, FALocInfo> Loc =
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std::make_pair(FALocInfo(FALocInfo::StackFrameLoc, FI), FALocInfo());
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FormalArgLocs.push_back(Loc);
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ArgOffset += ArgIncrement; // Move on to the next argument...
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}
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ArgValue= DAG.getCopyFromReg(Root, Reg, ObjectVT);
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ArgValues.push_back(ArgValue);
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NumXMMRegs += ObjXMMRegs;
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} else {
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// Create the frame index object for this incoming parameter...
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int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
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SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
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ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN,
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DAG.getSrcValue(NULL));
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ArgValues.push_back(ArgValue);
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ArgOffset += ArgIncrement; // Move on to the next argument...
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}
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}
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ArgValues.push_back(Root);
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// If the function takes variable number of arguments, make a frame index for
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// the start of the first vararg value... for expansion of llvm.va_start.
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if (F.isVarArg())
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if (MF.getFunction()->isVarArg())
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VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
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ReturnAddrIndex = 0; // No return address slot generated yet.
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BytesToPopOnReturn = 0; // Callee pops nothing.
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BytesCallerReserves = ArgOffset;
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// If this is a struct return on Darwin/X86, the callee pops the hidden struct
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// pointer.
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if (F.getCallingConv() == CallingConv::CSRet &&
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if (MF.getFunction()->getCallingConv() == CallingConv::CSRet &&
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Subtarget->isTargetDarwin())
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BytesToPopOnReturn = 4;
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}
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void X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG) {
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unsigned NumArgs = Op.Val->getNumValues() - 1;
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MachineFunction &MF = DAG.getMachineFunction();
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for (unsigned i = 0; i < NumArgs; ++i) {
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std::pair<FALocInfo, FALocInfo> Loc = FormalArgLocs[i];
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SDOperand ArgValue;
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if (Loc.first.Kind == FALocInfo::StackFrameLoc) {
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// Create the SelectionDAG nodes corresponding to a load from this
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// parameter.
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unsigned FI = FormalArgLocs[i].first.Loc;
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SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
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ArgValue = DAG.getLoad(Op.Val->getValueType(i),
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DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
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} else {
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// Must be a CopyFromReg
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ArgValue= DAG.getCopyFromReg(DAG.getEntryNode(), Loc.first.Loc,
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Loc.first.Typ);
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}
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FormalArgs.push_back(ArgValue);
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}
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// Provide a chain. Note that this isn't the right one, but it works as well
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// as before.
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FormalArgs.push_back(DAG.getEntryNode());
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// Return the new list of results.
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std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(),
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Op.Val->value_end());
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return DAG.getNode(ISD::MERGE_VALUES, RetVTs, ArgValues);
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}
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std::pair<SDOperand, SDOperand>
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@ -911,12 +871,13 @@ HowToPassFastCCArgument(MVT::ValueType ObjectVT,
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}
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}
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void
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X86TargetLowering::PreprocessFastCCArguments(std::vector<SDOperand> &Args,
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Function &F, SelectionDAG &DAG) {
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unsigned NumArgs = Args.size();
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SDOperand
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X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
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unsigned NumArgs = Op.Val->getNumValues()-1;
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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SDOperand Root = Op.getOperand(0);
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std::vector<SDOperand> ArgValues;
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// Add DAG nodes to load the arguments... On entry to a function the stack
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// frame looks like this:
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@ -935,94 +896,82 @@ X86TargetLowering::PreprocessFastCCArguments(std::vector<SDOperand> &Args,
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unsigned XMMArgRegs[] = { X86::XMM0, X86::XMM1, X86::XMM2 };
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for (unsigned i = 0; i < NumArgs; ++i) {
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SDOperand Op = Args[i];
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std::vector<SDOperand> Objs = getFormalArgObjects(Op);
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for (std::vector<SDOperand>::iterator I = Objs.begin(), E = Objs.end();
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I != E; ++I) {
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SDOperand Obj = *I;
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MVT::ValueType ObjectVT = Obj.getValueType();
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unsigned ArgIncrement = 4;
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unsigned ObjSize = 0;
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unsigned ObjIntRegs = 0;
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unsigned ObjXMMRegs = 0;
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MVT::ValueType ObjectVT = Op.getValue(i).getValueType();
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unsigned ArgIncrement = 4;
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unsigned ObjSize = 0;
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unsigned ObjIntRegs = 0;
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unsigned ObjXMMRegs = 0;
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HowToPassFastCCArgument(ObjectVT, NumIntRegs, NumXMMRegs,
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ObjSize, ObjIntRegs, ObjXMMRegs);
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if (ObjSize >= 8)
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ArgIncrement = ObjSize;
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HowToPassFastCCArgument(ObjectVT, NumIntRegs, NumXMMRegs,
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ObjSize, ObjIntRegs, ObjXMMRegs);
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if (ObjSize >= 8)
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ArgIncrement = ObjSize;
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unsigned Reg;
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std::pair<FALocInfo,FALocInfo> Loc = std::make_pair(FALocInfo(),
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FALocInfo());
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if (ObjIntRegs) {
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i1:
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case MVT::i8:
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Reg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
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X86::GR8RegisterClass);
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Loc.first.Kind = FALocInfo::LiveInRegLoc;
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Loc.first.Loc = Reg;
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Loc.first.Typ = MVT::i8;
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break;
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case MVT::i16:
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Reg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
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X86::GR16RegisterClass);
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Loc.first.Kind = FALocInfo::LiveInRegLoc;
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Loc.first.Loc = Reg;
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Loc.first.Typ = MVT::i16;
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break;
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case MVT::i32:
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Reg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::EAX,
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X86::GR32RegisterClass);
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Loc.first.Kind = FALocInfo::LiveInRegLoc;
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Loc.first.Loc = Reg;
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Loc.first.Typ = MVT::i32;
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break;
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case MVT::i64:
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Reg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::EAX,
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X86::GR32RegisterClass);
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Loc.first.Kind = FALocInfo::LiveInRegLoc;
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Loc.first.Loc = Reg;
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Loc.first.Typ = MVT::i32;
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if (ObjIntRegs == 2) {
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Reg = AddLiveIn(MF, X86::EDX, X86::GR32RegisterClass);
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Loc.second.Kind = FALocInfo::LiveInRegLoc;
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Loc.second.Loc = Reg;
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Loc.second.Typ = MVT::i32;
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}
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break;
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case MVT::v16i8:
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case MVT::v8i16:
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case MVT::v4i32:
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case MVT::v2i64:
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case MVT::v4f32:
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case MVT::v2f64:
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Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass);
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Loc.first.Kind = FALocInfo::LiveInRegLoc;
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Loc.first.Loc = Reg;
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Loc.first.Typ = ObjectVT;
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break;
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unsigned Reg;
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SDOperand ArgValue;
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if (ObjIntRegs || ObjXMMRegs) {
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i1:
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case MVT::i8:
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Reg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
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X86::GR8RegisterClass);
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ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i8);
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break;
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case MVT::i16:
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Reg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
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X86::GR16RegisterClass);
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ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i16);
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break;
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case MVT::i32:
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Reg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::EAX,
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X86::GR32RegisterClass);
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ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i32);
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break;
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case MVT::i64:
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Reg = AddLiveIn(MF, NumIntRegs ? X86::EDX : X86::EAX,
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X86::GR32RegisterClass);
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ArgValue = DAG.getCopyFromReg(Root, Reg, MVT::i32);
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if (ObjIntRegs == 2) {
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Reg = AddLiveIn(MF, X86::EDX, X86::GR32RegisterClass);
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SDOperand ArgValue2 = DAG.getCopyFromReg(Root, Reg, MVT::i32);
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ArgValue= DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
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}
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NumIntRegs += ObjIntRegs;
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NumXMMRegs += ObjXMMRegs;
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break;
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case MVT::v16i8:
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case MVT::v8i16:
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case MVT::v4i32:
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case MVT::v2i64:
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case MVT::v4f32:
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case MVT::v2f64:
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Reg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass);
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ArgValue = DAG.getCopyFromReg(Root, Reg, ObjectVT);
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break;
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}
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if (ObjSize) {
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int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
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if (ObjectVT == MVT::i64 && ObjIntRegs) {
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Loc.second.Kind = FALocInfo::StackFrameLoc;
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Loc.second.Loc = FI;
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} else {
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Loc.first.Kind = FALocInfo::StackFrameLoc;
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Loc.first.Loc = FI;
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}
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ArgOffset += ArgIncrement; // Move on to the next argument.
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}
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FormalArgLocs.push_back(Loc);
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NumIntRegs += ObjIntRegs;
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NumXMMRegs += ObjXMMRegs;
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}
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if (ObjSize) {
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// Create the SelectionDAG nodes corresponding to a load from this
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// parameter.
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int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
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SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
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if (ObjectVT == MVT::i64 && ObjIntRegs) {
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SDOperand ArgValue2 = DAG.getLoad(Op.Val->getValueType(i), Root, FIN,
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DAG.getSrcValue(NULL));
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ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
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} else
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ArgValue = DAG.getLoad(Op.Val->getValueType(i), Root, FIN,
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DAG.getSrcValue(NULL));
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ArgOffset += ArgIncrement; // Move on to the next argument.
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}
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ArgValues.push_back(ArgValue);
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}
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ArgValues.push_back(Root);
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// Make sure the instruction takes 8n+4 bytes to make sure the start of the
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// arguments and the arguments after the retaddr has been pushed are aligned.
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if ((ArgOffset & 7) == 0)
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@ -1034,7 +983,7 @@ X86TargetLowering::PreprocessFastCCArguments(std::vector<SDOperand> &Args,
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BytesCallerReserves = 0;
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// Finally, inform the code generator which regs we return values in.
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switch (getValueType(F.getReturnType())) {
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switch (getValueType(MF.getFunction()->getReturnType())) {
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default: assert(0 && "Unknown type!");
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case MVT::isVoid: break;
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case MVT::i1:
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@ -1052,7 +1001,7 @@ X86TargetLowering::PreprocessFastCCArguments(std::vector<SDOperand> &Args,
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MF.addLiveOut(X86::ST0);
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break;
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case MVT::Vector: {
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const PackedType *PTy = cast<PackedType>(F.getReturnType());
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const PackedType *PTy = cast<PackedType>(MF.getFunction()->getReturnType());
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MVT::ValueType EVT;
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MVT::ValueType LVT;
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unsigned NumRegs = getPackedTypeBreakdown(PTy, EVT, LVT);
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@ -1061,50 +1010,11 @@ X86TargetLowering::PreprocessFastCCArguments(std::vector<SDOperand> &Args,
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break;
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}
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}
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}
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void
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X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
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unsigned NumArgs = Op.Val->getNumValues()-1;
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MachineFunction &MF = DAG.getMachineFunction();
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for (unsigned i = 0; i < NumArgs; ++i) {
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MVT::ValueType VT = Op.Val->getValueType(i);
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std::pair<FALocInfo, FALocInfo> Loc = FormalArgLocs[i];
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SDOperand ArgValue;
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if (Loc.first.Kind == FALocInfo::StackFrameLoc) {
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// Create the SelectionDAG nodes corresponding to a load from this
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// parameter.
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SDOperand FIN = DAG.getFrameIndex(Loc.first.Loc, MVT::i32);
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ArgValue = DAG.getLoad(Op.Val->getValueType(i), DAG.getEntryNode(), FIN,
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DAG.getSrcValue(NULL));
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} else {
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// Must be a CopyFromReg
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ArgValue= DAG.getCopyFromReg(DAG.getEntryNode(), Loc.first.Loc,
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Loc.first.Typ);
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}
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if (Loc.second.Kind != FALocInfo::None) {
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SDOperand ArgValue2;
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if (Loc.second.Kind == FALocInfo::StackFrameLoc) {
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// Create the SelectionDAG nodes corresponding to a load from this
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// parameter.
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SDOperand FIN = DAG.getFrameIndex(Loc.second.Loc, MVT::i32);
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ArgValue2 = DAG.getLoad(Op.Val->getValueType(i), DAG.getEntryNode(),
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FIN, DAG.getSrcValue(NULL));
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} else {
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// Must be a CopyFromReg
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ArgValue2 = DAG.getCopyFromReg(DAG.getEntryNode(),
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Loc.second.Loc, Loc.second.Typ);
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}
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ArgValue = DAG.getNode(ISD::BUILD_PAIR, VT, ArgValue, ArgValue2);
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}
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FormalArgs.push_back(ArgValue);
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}
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// Provide a chain. Note that this isn't the right one, but it works as well
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// as before.
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FormalArgs.push_back(DAG.getEntryNode());
|
||||
// Return the new list of results.
|
||||
std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(),
|
||||
Op.Val->value_end());
|
||||
return DAG.getNode(ISD::MERGE_VALUES, RetVTs, ArgValues);
|
||||
}
|
||||
|
||||
std::pair<SDOperand, SDOperand>
|
||||
@ -3529,18 +3439,11 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
|
||||
|
||||
SDOperand
|
||||
X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
|
||||
if (FormalArgs.size() == 0) {
|
||||
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
|
||||
if (CC == CallingConv::Fast && EnableFastCC)
|
||||
LowerFastCCArguments(Op, DAG);
|
||||
else
|
||||
LowerCCCArguments(Op, DAG);
|
||||
}
|
||||
|
||||
// Return the new list of results.
|
||||
std::vector<MVT::ValueType> RetVTs(Op.Val->value_begin(),
|
||||
Op.Val->value_end());
|
||||
return DAG.getNode(ISD::MERGE_VALUES, RetVTs, FormalArgs);
|
||||
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
|
||||
if (CC == CallingConv::Fast && EnableFastCC)
|
||||
return LowerFastCCArguments(Op, DAG);
|
||||
else
|
||||
return LowerCCCArguments(Op, DAG);
|
||||
}
|
||||
|
||||
SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
|
||||
|
||||
@ -282,11 +282,6 @@ namespace llvm {
|
||||
///
|
||||
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
|
||||
|
||||
/// LowerArguments - This hook must be implemented to indicate how we should
|
||||
/// lower the arguments for the specified function, into the specified DAG.
|
||||
virtual std::vector<SDOperand>
|
||||
LowerArguments(Function &F, SelectionDAG &DAG);
|
||||
|
||||
/// LowerCallTo - This hook lowers an abstract call to a function into an
|
||||
/// actual call.
|
||||
virtual std::pair<SDOperand, SDOperand>
|
||||
@ -346,42 +341,15 @@ namespace llvm {
|
||||
/// X86ScalarSSE - Select between SSE2 or x87 floating point ops.
|
||||
bool X86ScalarSSE;
|
||||
|
||||
/// Formal arguments lowered to load and CopyFromReg ops.
|
||||
std::vector<SDOperand> FormalArgs;
|
||||
|
||||
/// Formal arguments locations (frame indices and registers).
|
||||
struct FALocInfo {
|
||||
enum FALocKind {
|
||||
None,
|
||||
StackFrameLoc,
|
||||
LiveInRegLoc,
|
||||
} Kind;
|
||||
|
||||
int Loc;
|
||||
MVT::ValueType Typ;
|
||||
|
||||
FALocInfo() : Kind(None), Loc(0), Typ(MVT::isVoid) {};
|
||||
FALocInfo(enum FALocKind k, int fi) : Kind(k), Loc(fi), Typ(MVT::isVoid) {};
|
||||
FALocInfo(enum FALocKind k, int r, MVT::ValueType vt)
|
||||
: Kind(k), Loc(r), Typ(vt) {};
|
||||
};
|
||||
|
||||
std::vector<std::pair<FALocInfo, FALocInfo> > FormalArgLocs;
|
||||
|
||||
// C Calling Convention implementation.
|
||||
void PreprocessCCCArguments(std::vector<SDOperand> &Args, Function &F,
|
||||
SelectionDAG &DAG);
|
||||
void LowerCCCArguments(SDOperand Op, SelectionDAG &DAG);
|
||||
SDOperand LowerCCCArguments(SDOperand Op, SelectionDAG &DAG);
|
||||
std::pair<SDOperand, SDOperand>
|
||||
LowerCCCCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
|
||||
bool isTailCall, unsigned CallingConv,
|
||||
SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
|
||||
|
||||
// Fast Calling Convention implementation.
|
||||
void
|
||||
PreprocessFastCCArguments(std::vector<SDOperand> &Args, Function &F,
|
||||
SelectionDAG &DAG);
|
||||
void
|
||||
SDOperand
|
||||
LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG);
|
||||
std::pair<SDOperand, SDOperand>
|
||||
LowerFastCCCallTo(SDOperand Chain, const Type *RetTy, bool isTailCall,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user