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[AVX512] Add masking variant for the FMA instructions
This change further evolves the base class AVX512_masking in order to make it suitable for the masking variants of the FMA instructions. Besides AVX512_masking there is now a new base class that instructions including FMAs can use: AVX512_masking_3src. With three-source (destructive) instructions one of the sources is already tied to the destination. This difference from AVX512_masking is captured by this new class. The common bits between _masking and _masking_3src are broken out into a new super class called AVX512_masking_common. As with valign, there is some corresponding restructuring of the underlying format classes. The idea is the same we want to derive from two classes essentially: one providing the format bits and another format-independent multiclass supplying the various masking and non-masking instruction variants. Existing fma tests in avx512-fma*.ll provide coverage here for the non-masking variants. For masking, the next patches in the series will add intrinsics and intrinsic tests. For AVX512_masking_3src to work, the (ins ...) dag has to be passed *without* the leading source operand that is tied to dst ($src1). This is necessary to properly construct the (ins ...) for the different variants. For the record, I did check that if $src is mistakenly included, you do get a fairly intuitive error message from the tablegen backend. Part of <rdar://problem/17688758> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215660 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Adam Nemet
parent
14bc045838
commit
265d201e19
@ -1,25 +1,28 @@
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multiclass AVX512_masking<bits<8> O, Format F, dag Outs, dag Ins,
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string OpcodeStr,
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string AttSrcAsm, string IntelSrcAsm,
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dag RHS, ValueType OpVT,
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RegisterClass RC, RegisterClass KRC> {
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// Common base class of AVX512_masking and AVX512_masking_3src.
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multiclass AVX512_masking_common<bits<8> O, Format F, dag Outs, dag Ins,
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dag MaskingIns, dag ZeroMaskingIns,
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string OpcodeStr,
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string AttSrcAsm, string IntelSrcAsm,
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dag RHS, dag MaskingRHS, ValueType OpVT,
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RegisterClass RC, RegisterClass KRC,
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string MaskingConstraint = ""> {
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def NAME: AVX512<O, F, Outs, Ins,
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OpcodeStr#" \t{"#AttSrcAsm#", $dst|"#
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"$dst, "#IntelSrcAsm#"}",
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[(set RC:$dst, RHS)]>;
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// Prefer over VMOV*rrk Pat<>
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let Constraints = "$src0 = $dst", AddedComplexity = 20 in
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def NAME#k: AVX512<O, F, Outs,
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!con((ins RC:$src0, KRC:$mask), Ins),
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let AddedComplexity = 20 in
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def NAME#k: AVX512<O, F, Outs, MaskingIns,
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OpcodeStr#" \t{"#AttSrcAsm#", $dst {${mask}}|"#
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"$dst {${mask}}, "#IntelSrcAsm#"}",
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[(set RC:$dst,
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(vselect KRC:$mask, RHS, RC:$src0))]>,
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EVEX_K;
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[(set RC:$dst, MaskingRHS)]>,
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EVEX_K {
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// In case of the 3src subclass this is overridden with a let.
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string Constraints = MaskingConstraint;
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}
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let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
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def NAME#kz: AVX512<O, F, Outs,
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!con((ins KRC:$mask), Ins),
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def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
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OpcodeStr#" \t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
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"$dst {${mask}} {z}, "#IntelSrcAsm#"}",
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[(set RC:$dst,
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@ -29,6 +32,40 @@ multiclass AVX512_masking<bits<8> O, Format F, dag Outs, dag Ins,
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EVEX_KZ;
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}
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// This multiclass generates the unconditional/non-masking, the masking and
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// the zero-masking variant of the instruction. In the masking case, the
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// perserved vector elements come from a new dummy input operand tied to $dst.
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multiclass AVX512_masking<bits<8> O, Format F, dag Outs, dag Ins,
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string OpcodeStr,
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string AttSrcAsm, string IntelSrcAsm,
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dag RHS, ValueType OpVT, RegisterClass RC,
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RegisterClass KRC> :
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AVX512_masking_common<O, F, Outs,
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Ins,
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!con((ins RC:$src0, KRC:$mask), Ins),
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!con((ins KRC:$mask), Ins),
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OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
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(vselect KRC:$mask, RHS, RC:$src0), OpVT, RC, KRC,
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"$src0 = $dst">;
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// Similar to AVX512_masking but in this case one of the source operands
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// ($src1) is already tied to $dst so we just use that for the preserved
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// vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
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// $src1.
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multiclass AVX512_masking_3src<bits<8> O, Format F, dag Outs, dag NonTiedIns,
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string OpcodeStr,
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string AttSrcAsm, string IntelSrcAsm,
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dag RHS, ValueType OpVT,
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RegisterClass RC, RegisterClass KRC> :
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AVX512_masking_common<O, F, Outs,
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!con((ins RC:$src1), NonTiedIns),
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!con((ins RC:$src1), !con((ins KRC:$mask),
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NonTiedIns)),
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!con((ins RC:$src1), !con((ins KRC:$mask),
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NonTiedIns)),
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OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
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(vselect KRC:$mask, RHS, RC:$src1), OpVT, RC, KRC>;
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// Bitcasts between 512-bit vector types. Return the original type since
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// no instruction is needed for the conversion
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let Predicates = [HasAVX512] in {
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@ -2955,11 +2992,13 @@ let Constraints = "$src1 = $dst" in {
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multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
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RegisterClass RC, X86MemOperand x86memop,
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PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
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string BrdcstStr, SDNode OpNode, ValueType OpVT> {
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def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
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string BrdcstStr, SDNode OpNode, ValueType OpVT,
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RegisterClass KRC> {
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defm r: AVX512_masking_3src<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src2, RC:$src3),
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OpcodeStr, "$src3, $src2", "$src2, $src3",
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(OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)), OpVT, RC, KRC>,
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AVX512FMA3Base;
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let mayLoad = 1 in
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def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
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@ -2979,53 +3018,53 @@ multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
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let ExeDomain = SSEPackedSingle in {
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defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fmadd, v16f32>, EVEX_V512,
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X86Fmadd, v16f32, VK16WM>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fmsub, v16f32>, EVEX_V512,
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X86Fmsub, v16f32, VK16WM>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fmaddsub, v16f32>,
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X86Fmaddsub, v16f32, VK16WM>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fmsubadd, v16f32>,
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X86Fmsubadd, v16f32, VK16WM>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fnmadd, v16f32>, EVEX_V512,
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X86Fnmadd, v16f32, VK16WM>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
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memopv16f32, f32mem, loadf32, "{1to16}",
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X86Fnmsub, v16f32>, EVEX_V512,
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X86Fnmsub, v16f32, VK16WM>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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}
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let ExeDomain = SSEPackedDouble in {
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defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fmadd, v8f64>, EVEX_V512,
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X86Fmadd, v8f64, VK8WM>, EVEX_V512,
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VEX_W, EVEX_CD8<64, CD8VF>;
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defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fmsub, v8f64>, EVEX_V512, VEX_W,
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X86Fmsub, v8f64, VK8WM>, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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X86Fmaddsub, v8f64, VK8WM>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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X86Fmsubadd, v8f64, VK8WM>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
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X86Fnmadd, v8f64, VK8WM>, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
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memopv8f64, f64mem, loadf64, "{1to8}",
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X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
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X86Fnmsub, v8f64, VK8WM>, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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}
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@ -722,7 +722,7 @@ class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
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Requires<[HasAVX512]>;
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class AVX512AIi8Base: TAPD {
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class AVX512AIi8Base : TAPD {
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Domain ExeDomain = SSEPackedInt;
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ImmType ImmT = Imm8;
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}
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@ -748,6 +748,7 @@ class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag>pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin>, T8PD,
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EVEX_4V, Requires<[HasAVX512]>;
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class AVX512FMA3Base : T8PD, EVEX_4V;
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class AVX512<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag>pattern, InstrItinClass itin = NoItinerary>
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