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https://github.com/c64scene-ar/llvm-6502.git
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Add bunch of reg-mem inst patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70725 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -134,125 +134,177 @@ let Defs = [SRW] in {
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let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
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// FIXME: Provide proper encoding!
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def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"add.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
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(implicit SRW)]>;
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def ADD8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"add.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
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(implicit SRW)]>;
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def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"add.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
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(implicit SRW)]>;
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}
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def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"add.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (add GR16:$src1, imm:$src2)),
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def ADD8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
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"add.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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def ADD16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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"add.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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def ADD8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
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"add.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (add GR8:$src1, imm:$src2)),
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(implicit SRW)]>;
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def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"add.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (add GR16:$src1, imm:$src2)),
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(implicit SRW)]>;
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let Uses = [SRW] in {
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let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y
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def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"addc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
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(implicit SRW)]>;
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def ADC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"addc.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (adde GR8:$src1, GR8:$src2)),
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(implicit SRW)]>;
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def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"addc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
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(implicit SRW)]>;
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} // isCommutable
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def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"addc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
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(implicit SRW)]>;
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def ADC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
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"addc.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (adde GR8:$src1, imm:$src2)),
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(implicit SRW)]>;
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def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"addc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
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(implicit SRW)]>;
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def ADC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
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"addc.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (adde GR8:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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def ADC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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"addc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (adde GR16:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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}
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let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
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def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"and.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
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(implicit SRW)]>;
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def AND8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"and.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
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(implicit SRW)]>;
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def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"and.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
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(implicit SRW)]>;
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}
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def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"and.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (and GR16:$src1, imm:$src2)),
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(implicit SRW)]>;
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def AND8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
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"and.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (and GR8:$src1, imm:$src2)),
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(implicit SRW)]>;
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def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"and.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (and GR16:$src1, imm:$src2)),
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(implicit SRW)]>;
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def AND8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
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"and.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (and GR8:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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def AND16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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"and.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (and GR16:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
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def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"xor.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
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(implicit SRW)]>;
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def XOR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"xor.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
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(implicit SRW)]>;
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def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"xor.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
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(implicit SRW)]>;
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}
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def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"xor.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
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(implicit SRW)]>;
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def XOR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
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"xor.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
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(implicit SRW)]>;
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def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"sub.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
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def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"xor.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
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(implicit SRW)]>;
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def XOR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
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"xor.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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def XOR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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"xor.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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def SUB8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"sub.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
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(implicit SRW)]>;
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def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"sub.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
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[(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
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(implicit SRW)]>;
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def SUB8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
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"sub.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
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(implicit SRW)]>;
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def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"sub.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
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(implicit SRW)]>;
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def SUB8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
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"sub.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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def SUB16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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"sub.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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let Uses = [SRW] in {
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def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"subc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
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(implicit SRW)]>;
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def SBC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"subc.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (sube GR8:$src1, GR8:$src2)),
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(implicit SRW)]>;
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def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"subc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
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(implicit SRW)]>;
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def SBC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
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"subc.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (sube GR8:$src1, imm:$src2)),
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(implicit SRW)]>;
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def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"subc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
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(implicit SRW)]>;
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def SBC8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
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def SBC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
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"subc.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (sube GR8:$src1, imm:$src2)),
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[(set GR8:$dst, (sube GR8:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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def SBC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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"subc.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (sube GR16:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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}
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@ -270,21 +322,27 @@ def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
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} // Defs = [SRW]
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let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
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def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"bis.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
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def OR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
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"bis.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
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def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"bis.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
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}
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def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"bis.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
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def OR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
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"bis.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
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def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
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"bis.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
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def OR8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
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"bis.b\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
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def OR16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
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"bis.w\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>;
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} // isTwoAddress = 1
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//===----------------------------------------------------------------------===//
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