6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-14 11:32:34 +00:00
Code Issues Projects Releases Wiki Activity

Add normal and trunc stores

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70724 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2009-05-03 13:06:26 +00:00
parent 36b6e533c1
commit 54f30d3fc9
3 changed files with 30 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/MSP430/MSP430ISelLowering.cpp
View File

@ -39,6 +39,7 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
// Set up the register classes.
addRegisterClass(MVT::i8, MSP430::GR8RegisterClass);
addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
// Compute derived properties from the register classes
@ -59,6 +60,9 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
// We don't have any truncstores
setTruncStoreAction(MVT::i16, MVT::i8, Expand);
setOperationAction(ISD::SRA, MVT::i16, Custom);
setOperationAction(ISD::RET, MVT::Other, Custom);
}

25
lib/Target/MSP430/MSP430InstrInfo.td
View File

@ -35,12 +35,17 @@ def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
// MSP430 Operand Definitions.
//===----------------------------------------------------------------------===//
// Address operand
// Address operands
def memsrc : Operand<i16> {
let PrintMethod = "printSrcMemOperand";
let MIOperandInfo = (ops i16imm, GR16);
}
def memdst : Operand<i16> {
let PrintMethod = "printSrcMemOperand";
let MIOperandInfo = (ops i16imm, GR16);
}
//===----------------------------------------------------------------------===//
// MSP430 Complex Pattern Definitions.
@ -106,6 +111,20 @@ def MOVZX16rm8 : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
"mov.b\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
def MOV8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
"mov.b\t{$src, $dst|$dst, $src}",
[(store (i8 imm:$src), addr:$dst)]>;
def MOV16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
"mov.w\t{$src, $dst|$dst, $src}",
[(store (i16 imm:$src), addr:$dst)]>;
def MOV8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
"mov.b\t{$src, $dst|$dst, $src}",
[(store GR8:$src, addr:$dst)]>;
def MOV16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
"mov.w\t{$src, $dst|$dst, $src}",
[(store GR16:$src, addr:$dst)]>;
//===----------------------------------------------------------------------===//
// Arithmetic Instructions
@ -273,3 +292,7 @@ def OR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
// extload
def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
// truncs
def : Pat<(i8 (trunc GR16:$src)),
(EXTRACT_SUBREG GR16:$src, subreg_8bit)>;

2
lib/Target/MSP430/MSP430RegisterInfo.td
View File

@ -65,6 +65,8 @@ def : SubRegSet<1, [PCW, SPW, SRW, CGW, FPW,
[PCB, SPB, SRB, CGB, FPB,
R5B, R6B, R7B, R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
def subreg_8bit : PatLeaf<(i32 1)>;
def GR8 : RegisterClass<"MSP430", [i8], 8,
// Volatile registers
[R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B,