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https://github.com/c64scene-ar/llvm-6502.git
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Add normal and trunc stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70724 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -39,6 +39,7 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
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TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
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// Set up the register classes.
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addRegisterClass(MVT::i8, MSP430::GR8RegisterClass);
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addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
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// Compute derived properties from the register classes
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@ -59,6 +60,9 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
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setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
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setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
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// We don't have any truncstores
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setTruncStoreAction(MVT::i16, MVT::i8, Expand);
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setOperationAction(ISD::SRA, MVT::i16, Custom);
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setOperationAction(ISD::RET, MVT::Other, Custom);
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}
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@ -35,12 +35,17 @@ def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
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// MSP430 Operand Definitions.
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//===----------------------------------------------------------------------===//
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// Address operand
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// Address operands
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def memsrc : Operand<i16> {
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let PrintMethod = "printSrcMemOperand";
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let MIOperandInfo = (ops i16imm, GR16);
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}
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def memdst : Operand<i16> {
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let PrintMethod = "printSrcMemOperand";
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let MIOperandInfo = (ops i16imm, GR16);
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}
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//===----------------------------------------------------------------------===//
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// MSP430 Complex Pattern Definitions.
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@ -106,6 +111,20 @@ def MOVZX16rm8 : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
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"mov.b\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (zextloadi16i8 addr:$src))]>;
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def MOV8mi : Pseudo<(outs), (ins memdst:$dst, i8imm:$src),
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"mov.b\t{$src, $dst|$dst, $src}",
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[(store (i8 imm:$src), addr:$dst)]>;
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def MOV16mi : Pseudo<(outs), (ins memdst:$dst, i16imm:$src),
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"mov.w\t{$src, $dst|$dst, $src}",
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[(store (i16 imm:$src), addr:$dst)]>;
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def MOV8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
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"mov.b\t{$src, $dst|$dst, $src}",
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[(store GR8:$src, addr:$dst)]>;
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def MOV16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
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"mov.w\t{$src, $dst|$dst, $src}",
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[(store GR16:$src, addr:$dst)]>;
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions
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@ -273,3 +292,7 @@ def OR8ri : Pseudo<(outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
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// extload
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def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
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// truncs
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def : Pat<(i8 (trunc GR16:$src)),
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(EXTRACT_SUBREG GR16:$src, subreg_8bit)>;
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@ -65,6 +65,8 @@ def : SubRegSet<1, [PCW, SPW, SRW, CGW, FPW,
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[PCB, SPB, SRB, CGB, FPB,
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R5B, R6B, R7B, R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
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def subreg_8bit : PatLeaf<(i32 1)>;
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def GR8 : RegisterClass<"MSP430", [i8], 8,
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// Volatile registers
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[R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B,
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