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Fix broken CHECK lines

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201479 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nico Rieck 2014-02-16 07:31:05 +00:00
parent 5a39da0a6f
commit 268e96a8a6
12 changed files with 25 additions and 25 deletions
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2
test/Analysis/CostModel/ARM/cast.ll
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@ -528,7 +528,7 @@ define i32 @casts() {
%r242 = uitofp <16 x i8> undef to <16 x double> %r242 = uitofp <16 x i8> undef to <16 x double>
; CHECK: cost of 64 {{.*}} sitofp ; CHECK: cost of 64 {{.*}} sitofp
%r243 = sitofp <16 x i8> undef to <16 x double> %r243 = sitofp <16 x i8> undef to <16 x double>
; C4ECK: cost of 64 {{.*}} uitofp ; CHECK: cost of 64 {{.*}} uitofp
%r244 = uitofp <16 x i16> undef to <16 x double> %r244 = uitofp <16 x i16> undef to <16 x double>
; CHECK: cost of 64 {{.*}} sitofp ; CHECK: cost of 64 {{.*}} sitofp
%r245 = sitofp <16 x i16> undef to <16 x double> %r245 = sitofp <16 x i16> undef to <16 x double>

2
test/CodeGen/AArch64/fcvt-int.ll
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@ -69,7 +69,7 @@ define float @test_i32tofloat(i32 %in) {
; CHECK-DAG: scvtf [[SIG:s[0-9]+]], {{w[0-9]+}} ; CHECK-DAG: scvtf [[SIG:s[0-9]+]], {{w[0-9]+}}
%res = fsub float %signed, %unsigned %res = fsub float %signed, %unsigned
; CHECL: fsub {{s[0-9]+}}, [[SIG]], [[UNSIG]] ; CHECK: fsub {{s[0-9]+}}, [[SIG]], [[UNSIG]]
ret float %res ret float %res
; CHECK: ret ; CHECK: ret
} }

8
test/CodeGen/ARM/2011-10-26-memset-inline.ll
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@ -6,10 +6,10 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-
target triple = "thumbv7-apple-ios5.0.0" target triple = "thumbv7-apple-ios5.0.0"
; CHECK-GENERIC: strb ; CHECK-GENERIC: strb
; CHECK-GENERIT-NEXT: strb ; CHECK-GENERIC-NEXT: strb
; CHECK-GENERIT-NEXT: strb ; CHECK-GENERIC-NEXT: strb
; CHECK-GENERIT-NEXT: strb ; CHECK-GENERIC-NEXT: strb
; CHECK-GENERIT-NEXT: strb ; CHECK-GENERIC-NEXT: strb
; CHECK-UNALIGNED: strb ; CHECK-UNALIGNED: strb
; CHECK-UNALIGNED: str ; CHECK-UNALIGNED: str
define void @foo(i8* nocapture %c) nounwind optsize { define void @foo(i8* nocapture %c) nounwind optsize {

6
test/CodeGen/ARM/build-attributes.ll
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@ -283,8 +283,8 @@
; CORTEX-A9-MP: .eabi_attribute 23, 3 ; CORTEX-A9-MP: .eabi_attribute 23, 3
; CORTEX-A9-MP: .eabi_attribute 24, 1 ; CORTEX-A9-MP: .eabi_attribute 24, 1
; CORTEX-A9-MP: .eabi_attribute 25, 1 ; CORTEX-A9-MP: .eabi_attribute 25, 1
; CORTEX-A9-NOT: .eabi_attribute 27 ; CORTEX-A9-MP-NOT: .eabi_attribute 27
; CORTEX-A9-NOT: .eabi_attribute 28 ; CORTEX-A9-MP-NOT: .eabi_attribute 28
; CORTEX-A9-MP: .eabi_attribute 36, 1 ; CORTEX-A9-MP: .eabi_attribute 36, 1
; CORTEX-A9-MP: .eabi_attribute 42, 1 ; CORTEX-A9-MP: .eabi_attribute 42, 1
; CORTEX-A9-MP: .eabi_attribute 68, 1 ; CORTEX-A9-MP: .eabi_attribute 68, 1
@ -401,7 +401,7 @@
; CORTEX-M4-HARD: .eabi_attribute 36, 1 ; CORTEX-M4-HARD: .eabi_attribute 36, 1
; CORTEX-M4-HARD-NOT: .eabi_attribute 42 ; CORTEX-M4-HARD-NOT: .eabi_attribute 42
; CORTEX-M4-HARD-NOT: .eabi_attribute 44 ; CORTEX-M4-HARD-NOT: .eabi_attribute 44
; CORTEX-M4-HRAD-NOT: .eabi_attribute 68 ; CORTEX-M4-HARD-NOT: .eabi_attribute 68
; CORTEX-R5: .cpu cortex-r5 ; CORTEX-R5: .cpu cortex-r5
; CORTEX-R5: .eabi_attribute 6, 10 ; CORTEX-R5: .eabi_attribute 6, 10

12
test/CodeGen/ARM/constantfp.ll
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@ -15,7 +15,7 @@ define arm_aapcs_vfpcc float @test_vmov_imm() {
; CHECK: vmov.i32 d0, #0 ; CHECK: vmov.i32 d0, #0
; CHECK-NONEON-LABEL: test_vmov_imm: ; CHECK-NONEON-LABEL: test_vmov_imm:
; CHECK_NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}} ; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
ret float 0.0 ret float 0.0
} }
@ -24,7 +24,7 @@ define arm_aapcs_vfpcc float @test_vmvn_imm() {
; CHECK: vmvn.i32 d0, #0xb0000000 ; CHECK: vmvn.i32 d0, #0xb0000000
; CHECK-NONEON-LABEL: test_vmvn_imm: ; CHECK-NONEON-LABEL: test_vmvn_imm:
; CHECK_NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}} ; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
ret float 8589934080.0 ret float 8589934080.0
} }
@ -33,7 +33,7 @@ define arm_aapcs_vfpcc double @test_vmov_f64() {
; CHECK: vmov.f64 d0, #1.0 ; CHECK: vmov.f64 d0, #1.0
; CHECK-NONEON-LABEL: test_vmov_f64: ; CHECK-NONEON-LABEL: test_vmov_f64:
; CHECK_NONEON: vmov.f64 d0, #1.0 ; CHECK-NONEON: vmov.f64 d0, #1.0
ret double 1.0 ret double 1.0
} }
@ -43,7 +43,7 @@ define arm_aapcs_vfpcc double @test_vmov_double_imm() {
; CHECK: vmov.i32 d0, #0 ; CHECK: vmov.i32 d0, #0
; CHECK-NONEON-LABEL: test_vmov_double_imm: ; CHECK-NONEON-LABEL: test_vmov_double_imm:
; CHECK_NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} ; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
ret double 0.0 ret double 0.0
} }
@ -52,7 +52,7 @@ define arm_aapcs_vfpcc double @test_vmvn_double_imm() {
; CHECK: vmvn.i32 d0, #0xb0000000 ; CHECK: vmvn.i32 d0, #0xb0000000
; CHECK-NONEON-LABEL: test_vmvn_double_imm: ; CHECK-NONEON-LABEL: test_vmvn_double_imm:
; CHECK_NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} ; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
ret double 0x4fffffff4fffffff ret double 0x4fffffff4fffffff
} }
@ -63,6 +63,6 @@ define arm_aapcs_vfpcc double @test_notvmvn_double_imm() {
; CHECK: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} ; CHECK: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
; CHECK-NONEON-LABEL: test_notvmvn_double_imm: ; CHECK-NONEON-LABEL: test_notvmvn_double_imm:
; CHECK_NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} ; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
ret double 0x4fffffffffffffff ret double 0x4fffffffffffffff
} }

8
test/CodeGen/ARM/debug-frame-large-stack.ll
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@ -28,10 +28,10 @@ define void @test1() {
; CHECK-ARM: sub sp, sp, #256 ; CHECK-ARM: sub sp, sp, #256
; CHECK-ARM: .cfi_endproc ; CHECK-ARM: .cfi_endproc
; CHECK-ARM-FP_ELIM-LABEL: test1: ; CHECK-ARM-FP-ELIM-LABEL: test1:
; CHECK-ARM-FP_ELIM: .cfi_startproc ; CHECK-ARM-FP-ELIM: .cfi_startproc
; CHECK-ARM-FP_ELIM: sub sp, sp, #256 ; CHECK-ARM-FP-ELIM: sub sp, sp, #256
; CHECK-ARM-FP_ELIM: .cfi_endproc ; CHECK-ARM-FP-ELIM: .cfi_endproc
define void @test2() { define void @test2() {
%tmp = alloca [ 4168 x i8 ] , align 4 %tmp = alloca [ 4168 x i8 ] , align 4

2
test/CodeGen/Hexagon/packetize_cond_inst.ll
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@ -12,7 +12,7 @@ target triple = "hexagon-unknown--elf"
; } ; }
; CHECK: cmp ; CHECK: cmp
; CHECK-NEXT: add ; CHECK-NEXT: add
; CHECH-NEXT: add ; CHECK-NEXT: add
define i32 @ifcnv_add(i32, i32, i32) nounwind readnone { define i32 @ifcnv_add(i32, i32, i32) nounwind readnone {
%4 = icmp sgt i32 %2, %1 %4 = icmp sgt i32 %2, %1
br i1 %4, label %5, label %7 br i1 %4, label %5, label %7

2
test/CodeGen/X86/2011-05-09-loaduse.ll
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@ -1,7 +1,7 @@
; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s ; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s
;CHECK-LABEL: test: ;CHECK-LABEL: test:
;CHECK-not: pshufd ;CHECK-NOT: pshufd
;CHECK: ret ;CHECK: ret
define float @test(<4 x float>* %A) nounwind { define float @test(<4 x float>* %A) nounwind {
entry: entry:

2
test/CodeGen/X86/tbm-intrinsics-x86_64.ll
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@ -34,7 +34,7 @@ declare i64 @llvm.x86.tbm.bextri.u64(i64, i64) nounwind readnone
define i64 @test_x86_tbm_bextri_u64_m(i64* nocapture %a) nounwind readonly { define i64 @test_x86_tbm_bextri_u64_m(i64* nocapture %a) nounwind readonly {
entry: entry:
; CHECK-LABEl: test_x86_tbm_bextri_u64_m: ; CHECK-LABEL: test_x86_tbm_bextri_u64_m:
; CHECK-NOT: mov ; CHECK-NOT: mov
; CHECK: bextr $ ; CHECK: bextr $
%tmp1 = load i64* %a, align 8 %tmp1 = load i64* %a, align 8

2
test/CodeGen/X86/vector-gep.ll
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@ -34,7 +34,7 @@ entry:
;CHECK-LABEL: AGEP2: ;CHECK-LABEL: AGEP2:
define i32 @AGEP2(<4 x i32*> %param, <4 x i32> %off) nounwind { define i32 @AGEP2(<4 x i32*> %param, <4 x i32> %off) nounwind {
entry: entry:
;CHECK_LABEL: AGEP2 ;CHECK-LABEL: AGEP2
;CHECK: vpslld $2 ;CHECK: vpslld $2
;CHECK-NEXT: vpadd ;CHECK-NEXT: vpadd
%A2 = getelementptr <4 x i32*> %param, <4 x i32> %off %A2 = getelementptr <4 x i32*> %param, <4 x i32> %off

2
test/MC/ELF/local-reloc.s
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@ -6,7 +6,7 @@
movl foo, %r14d movl foo, %r14d
foo: foo:
// CHECKT: Relocations [ // CHECK: Relocations [
// CHECK: Section (2) .rela.text { // CHECK: Section (2) .rela.text {
// CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_32S .text 0x{{[^ ]+}} // CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_32S .text 0x{{[^ ]+}}
// CHECK-NEXT: } // CHECK-NEXT: }

2
test/Transforms/DeadArgElim/deadexternal.ll
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@ -32,7 +32,7 @@ entry:
%i = alloca i32, align 4 %i = alloca i32, align 4
store volatile i32 10, i32* %i, align 4 store volatile i32 10, i32* %i, align 4
; CHECK: %tmp = load volatile i32* %i, align 4 ; CHECK: %tmp = load volatile i32* %i, align 4
; CHECK-next: call void @f(i32 undef) ; CHECK-NEXT: call void @f(i32 undef)
%tmp = load volatile i32* %i, align 4 %tmp = load volatile i32* %i, align 4
call void @f(i32 %tmp) call void @f(i32 %tmp)
ret void ret void