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Add or reg-reg pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75914 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -69,5 +69,13 @@ def ADD64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
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[(set GR64:$dst, (add GR64:$src1, imm:$src2)),
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(implicit PSW)]>;
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let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
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// FIXME: Provide proper encoding!
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def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
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"ogr\t{$dst, $src2}",
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[(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
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}
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// FIXME: provide patterns for masked or-with-imm
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} // Defs = [PSW]
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} // isTwoAddress = 1
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6
test/CodeGen/SystemZ/02-RetOr.ll
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6
test/CodeGen/SystemZ/02-RetOr.ll
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@ -0,0 +1,6 @@
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; RUN: llvm-as < %s | llc
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define i64 @foo(i64 %a, i64 %b) {
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entry:
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%c = or i64 %a, %b
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ret i64 %c
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}
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9
test/CodeGen/SystemZ/02-RetOrImm.ll
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9
test/CodeGen/SystemZ/02-RetOrImm.ll
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@ -0,0 +1,9 @@
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; RUN: llvm-as < %s | llc
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define i64 @foo(i64 %a, i64 %b) {
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entry:
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%c = or i64 %a, 1
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ret i64 %c
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}
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; FIXME: SystemZ has 4 or reg-imm instructions depending on imm,
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; we need to support them someday.
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