mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-02 02:55:35 +00:00
Fix mips' long branch pass.
Instructions emitted to compute branch offsets now use immediate operands instead of symbolic labels. This change was needed because there were problems when R_MIPS_HI16/LO16 relocations were used to make shared objects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162731 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
8dc440a46a
commit
273956d8c6
@ -10,6 +10,10 @@
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// This pass expands a branch or jump instruction into a long branch if its
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// offset is too large to fit into its immediate field.
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//
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// FIXME:
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// 1. Fix pc-region jump instructions which cross 256MB segment boundaries.
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// 2. If program has inline assembly statements whose size cannot be
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// determined accurately, load branch target addresses from the GOT.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-long-branch"
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@ -48,7 +52,7 @@ namespace {
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typedef MachineBasicBlock::reverse_iterator ReverseIter;
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struct MBBInfo {
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uint64_t Size;
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uint64_t Size, Address;
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bool HasLongBranch;
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MachineInstr *Br;
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@ -61,7 +65,10 @@ namespace {
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static char ID;
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MipsLongBranch(TargetMachine &tm)
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: MachineFunctionPass(ID), TM(tm),
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TII(static_cast<const MipsInstrInfo*>(tm.getInstrInfo())) {}
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TII(static_cast<const MipsInstrInfo*>(tm.getInstrInfo())),
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IsPIC(TM.getRelocationModel() == Reloc::PIC_),
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ABI(TM.getSubtarget<MipsSubtarget>().getTargetABI()),
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LongBranchSeqSize(!IsPIC ? 2 : (ABI == MipsSubtarget::N64 ? 13 : 9)) {}
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virtual const char *getPassName() const {
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return "Mips Long Branch";
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@ -81,6 +88,9 @@ namespace {
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const MipsInstrInfo *TII;
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MachineFunction *MF;
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SmallVector<MBBInfo, 16> MBBInfos;
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bool IsPIC;
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unsigned ABI;
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unsigned LongBranchSeqSize;
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};
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char MipsLongBranch::ID = 0;
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@ -230,12 +240,6 @@ void MipsLongBranch::replaceBranch(MachineBasicBlock &MBB, Iter Br,
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// Expand branch instructions to long branches.
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void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
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I.HasLongBranch = true;
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bool IsPIC = TM.getRelocationModel() == Reloc::PIC_;
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unsigned ABI = TM.getSubtarget<MipsSubtarget>().getTargetABI();
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bool N64 = ABI == MipsSubtarget::N64;
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MachineBasicBlock::iterator Pos;
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MachineBasicBlock *MBB = I.Br->getParent(), *TgtMBB = getTargetMBB(*I.Br);
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DebugLoc DL = I.Br->getDebugLoc();
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@ -248,101 +252,104 @@ void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
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MBB->addSuccessor(LongBrMBB);
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if (IsPIC) {
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// $longbr:
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// addiu $sp, $sp, -regsize * 2
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// sw $ra, 0($sp)
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// bal $baltgt
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// sw $a3, regsize($sp)
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// $baltgt:
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// lui $a3, %hi($baltgt)
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// lui $at, %hi($tgt)
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// addiu $a3, $a3, %lo($baltgt)
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// addiu $at, $at, %lo($tgt)
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// subu $at, $at, $a3
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// addu $at, $ra, $at
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//
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// if n64:
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// lui $a3, %highest($baltgt)
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// lui $ra, %highest($tgt)
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// addiu $a3, $a3, %higher($baltgt)
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// addiu $ra, $ra, %higher($tgt)
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// dsll $a3, $a3, 32
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// dsll $ra, $ra, 32
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// subu $at, $at, $a3
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// addu $at, $at, $ra
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//
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// lw $ra, 0($sp)
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// lw $a3, regsize($sp)
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// jr $at
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// addiu $sp, $sp, regsize * 2
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// $fallthrough:
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//
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MF->getInfo<MipsFunctionInfo>()->setEmitNOAT();
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MachineBasicBlock *BalTgtMBB = MF->CreateMachineBasicBlock(BB);
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MF->insert(FallThroughMBB, BalTgtMBB);
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LongBrMBB->addSuccessor(BalTgtMBB);
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BalTgtMBB->addSuccessor(TgtMBB);
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int RegSize = N64 ? 8 : 4;
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unsigned AT = N64 ? Mips::AT_64 : Mips::AT;
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unsigned A3 = N64 ? Mips::A3_64 : Mips::A3;
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unsigned SP = N64 ? Mips::SP_64 : Mips::SP;
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unsigned RA = N64 ? Mips::RA_64 : Mips::RA;
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unsigned Load = N64 ? Mips::LD_P8 : Mips::LW;
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unsigned Store = N64 ? Mips::SD_P8 : Mips::SW;
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unsigned LUi = N64 ? Mips::LUi64 : Mips::LUi;
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unsigned ADDiu = N64 ? Mips::DADDiu : Mips::ADDiu;
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unsigned ADDu = N64 ? Mips::DADDu : Mips::ADDu;
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unsigned SUBu = N64 ? Mips::SUBu : Mips::SUBu;
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unsigned JR = N64 ? Mips::JR64 : Mips::JR;
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uint64_t TgtAddress = MBBInfos[TgtMBB->getNumber()].Address;
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uint64_t Offset = TgtAddress - (I.Address + I.Size - 20);
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uint64_t Lo = Offset & 0xffff;
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uint64_t Hi = ((Offset + 0x8000) >> 16) & 0xffff;
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Pos = LongBrMBB->begin();
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if (ABI != MipsSubtarget::N64) {
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// $longbr:
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// addiu $sp, $sp, -8
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// sw $ra, 0($sp)
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// bal $baltgt
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// lui $at, %hi($tgt - $baltgt)
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// $baltgt:
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// addiu $at, $at, %lo($tgt - $baltgt)
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// addu $at, $ra, $at
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// lw $ra, 0($sp)
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// jr $at
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// addiu $sp, $sp, 8
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// $fallthrough:
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//
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BuildMI(*LongBrMBB, Pos, DL, TII->get(ADDiu), SP).addReg(SP)
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.addImm(-RegSize * 2);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Store)).addReg(RA).addReg(SP)
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.addImm(0);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Store)).addReg(A3).addReg(SP)
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.addImm(RegSize)->setIsInsideBundle();
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Pos = LongBrMBB->begin();
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Pos = BalTgtMBB->begin();
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
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.addReg(Mips::SP).addImm(-8);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
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.addReg(Mips::SP).addImm(0);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LUi), Mips::AT).addImm(Hi)
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->setIsInsideBundle();
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(LUi), A3)
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.addMBB(BalTgtMBB, MipsII::MO_ABS_HI);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(LUi), AT)
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.addMBB(TgtMBB, MipsII::MO_ABS_HI);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(ADDiu), A3).addReg(A3)
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.addMBB(BalTgtMBB, MipsII::MO_ABS_LO);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(ADDiu), AT).addReg(AT)
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.addMBB(TgtMBB, MipsII::MO_ABS_LO);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(SUBu), AT).addReg(AT).addReg(A3);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(ADDu), AT).addReg(RA).addReg(AT);
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Pos = BalTgtMBB->begin();
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if (N64) {
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(LUi), A3)
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.addMBB(BalTgtMBB, MipsII::MO_HIGHEST);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(LUi), RA)
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.addMBB(TgtMBB, MipsII::MO_HIGHEST);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(ADDiu), A3).addReg(A3)
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.addMBB(BalTgtMBB, MipsII::MO_HIGHER);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(ADDiu), RA).addReg(RA)
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.addMBB(TgtMBB, MipsII::MO_HIGHER);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DSLL), A3).addReg(A3)
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.addImm(32);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DSLL), RA).addReg(RA)
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.addImm(32);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(SUBu), AT).addReg(AT).addReg(A3);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(ADDu), AT).addReg(AT).addReg(RA);
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I.Size += 4 * 8;
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::AT)
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.addReg(Mips::AT).addImm(Lo);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
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.addReg(Mips::RA).addReg(Mips::AT);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
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.addReg(Mips::SP).addImm(0);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR)).addReg(Mips::AT);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
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.addReg(Mips::SP).addImm(8)->setIsInsideBundle();
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} else {
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// $longbr:
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// daddiu $sp, $sp, -16
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// sd $ra, 0($sp)
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// lui64 $at, %highest($tgt - $baltgt)
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// daddiu $at, $at, %higher($tgt - $baltgt)
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// dsll $at, $at, 16
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// daddiu $at, $at, %hi($tgt - $baltgt)
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// bal $baltgt
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// dsll $at, $at, 16
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// $baltgt:
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// daddiu $at, $at, %lo($tgt - $baltgt)
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// daddu $at, $ra, $at
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// ld $ra, 0($sp)
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// jr64 $at
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// daddiu $sp, $sp, 16
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// $fallthrough:
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//
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uint64_t Higher = ((Offset + 0x80008000) >> 32) & 0xffff;
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uint64_t Highest = ((Offset + 0x800080008000LL) >> 48) & 0xffff;
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Pos = LongBrMBB->begin();
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
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.addReg(Mips::SP_64).addImm(-16);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD)).addReg(Mips::RA_64)
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.addReg(Mips::SP_64).addImm(0);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LUi64), Mips::AT_64)
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.addImm(Highest);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::AT_64)
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.addReg(Mips::AT_64).addImm(Higher);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
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.addReg(Mips::AT_64).addImm(16);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::AT_64)
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.addReg(Mips::AT_64).addImm(Hi);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
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.addReg(Mips::AT_64).addImm(16)->setIsInsideBundle();
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Pos = BalTgtMBB->begin();
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::AT_64)
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.addReg(Mips::AT_64).addImm(Lo);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64)
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.addReg(Mips::RA_64).addReg(Mips::AT_64);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
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.addReg(Mips::SP_64).addImm(0);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR64)).addReg(Mips::AT_64);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
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.addReg(Mips::SP_64).addImm(16)->setIsInsideBundle();
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}
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Load), RA).addReg(SP).addImm(0);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Load), A3).addReg(SP).addImm(RegSize);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(JR)).addReg(AT);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(ADDiu), SP).addReg(SP)
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.addImm(RegSize * 2)->setIsInsideBundle();
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I.Size += 4 * 14;
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} else {
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// $longbr:
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// j $tgt
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@ -353,7 +360,6 @@ void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
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LongBrMBB->addSuccessor(TgtMBB);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::J)).addMBB(TgtMBB);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::NOP))->setIsInsideBundle();
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I.Size += 4 * 2;
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}
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if (I.Br->isUnconditionalBranch()) {
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@ -401,19 +407,36 @@ bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) {
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if (!I->Br || I->HasLongBranch)
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continue;
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if (!ForceLongBranch)
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// Check if offset fits into 16-bit immediate field of branches.
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if (isInt<16>(computeOffset(I->Br) / 4))
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continue;
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// Check if offset fits into 16-bit immediate field of branches.
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if (!ForceLongBranch && isInt<16>(computeOffset(I->Br) / 4))
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continue;
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expandToLongBranch(*I);
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I->HasLongBranch = true;
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I->Size += LongBranchSeqSize;
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++LongBranches;
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EverMadeChange = MadeChange = true;
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}
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}
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if (EverMadeChange)
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MF->RenumberBlocks();
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if (!EverMadeChange)
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return true;
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// Compute basic block addresses.
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if (TM.getRelocationModel() == Reloc::PIC_) {
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MF->getInfo<MipsFunctionInfo>()->setEmitNOAT();
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uint64_t Address = 0;
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for (I = MBBInfos.begin(); I != E; ++I, Address += I->Size)
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I->Address = Address;
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}
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// Do the expansion.
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for (I = MBBInfos.begin(); I != E; ++I)
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if (I->HasLongBranch)
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expandToLongBranch(*I);
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MF->RenumberBlocks();
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return true;
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}
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@ -6,9 +6,15 @@
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define void @foo1(i32 %s) nounwind {
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entry:
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; O32: bal
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; O32: lui $at, 0
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; O32: addiu $at, $at, {{[0-9]+}}
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; N64: lui $at, 0
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; N64: daddiu $at, $at, 0
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; N64: dsll $at, $at, 16
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; N64: daddiu $at, $at, 0
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; N64: bal
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; N64: highest
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; N64: higher
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; N64: dsll $at, $at, 16
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; N64: daddiu $at, $at, {{[0-9]+}}
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%tobool = icmp eq i32 %s, 0
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br i1 %tobool, label %if.end, label %if.then
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@ -1,5 +1,8 @@
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; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 -force-mips-long-branch -filetype=obj < %s -o - | elf-dump --dump-section-data | FileCheck %s
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; DISABLE: llc -march=mips64el -mcpu=mips64 -mattr=n64 -force-mips-long-branch -filetype=obj < %s -o - | elf-dump --dump-section-data | FileCheck %s
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; RUN: false
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; XFAIL: *
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; Disabled because currently we don't have a way to generate these relocations.
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;
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; Check that the R_MIPS_HIGHER and R_MIPS_HIGHEST relocations were created.
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; CHECK: ('r_type', 0x1d)
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