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Silence GCC warnings and make an array const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138706 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -5216,7 +5216,7 @@ struct AddSubFlagsOpcodePair {
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unsigned MachineOpc;
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};
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static AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
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static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
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{ARM::ADCSri, ARM::ADCri},
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{ARM::ADCSrr, ARM::ADCrr},
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{ARM::ADCSrsi, ARM::ADCrsi},
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@ -5256,7 +5256,7 @@ bool ARMTargetLowering::RemapAddSubWithFlags(MachineInstr *MI,
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// the tiny opcode table is not costly.
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static const int NPairs =
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sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair);
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for (AddSubFlagsOpcodePair *Pair = &AddSubFlagsOpcodeMap[0],
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for (const AddSubFlagsOpcodePair *Pair = &AddSubFlagsOpcodeMap[0],
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*End = &AddSubFlagsOpcodeMap[NPairs]; Pair != End; ++Pair) {
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if (OldOpc == Pair->PseudoOpc) {
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NewOpc = Pair->MachineOpc;
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@ -5303,7 +5303,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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Offset = -Offset;
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MachineMemOperand *MMO = *MI->memoperands_begin();
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MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc))
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BuildMI(*BB, MI, dl, TII->get(NewOpc))
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.addOperand(MI->getOperand(0)) // Rn_wb
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.addOperand(MI->getOperand(1)) // Rt
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.addOperand(MI->getOperand(2)) // Rn
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@ -10345,9 +10345,8 @@ static void ReplaceATOMIC_LOAD(SDNode *Node,
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// FIXME: On 32-bit, load -> fild or movq would be more efficient
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// (The only way to get a 16-byte load is cmpxchg16b)
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// FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
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SDValue Zero = DAG.getConstant(0, cast<AtomicSDNode>(Node)->getMemoryVT());
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SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
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cast<AtomicSDNode>(Node)->getMemoryVT(),
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SDValue Zero = DAG.getConstant(0, VT);
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SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
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Node->getOperand(0),
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Node->getOperand(1), Zero, Zero,
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cast<AtomicSDNode>(Node)->getMemOperand(),
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@ -10425,7 +10424,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
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}
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case ISD::ATOMIC_CMP_SWAP: {
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EVT T = N->getValueType(0);
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assert (T == MVT::i64 || T == MVT::i128 && "can only expand cmpxchg pair");
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assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
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bool Regs64bit = T == MVT::i128;
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EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
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SDValue cpInL, cpInH;
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