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- Two minor improvements to the MachineInstr class to reduce footprint and
overhead: Merge 3 parallel vectors into 1, change regsUsed hash_set to be a bitvector. Sped up LLC a little less than 10% in a debug build! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4261 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -12,7 +12,6 @@
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#include "llvm/Target/MachineInstrInfo.h"
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#include "llvm/Annotation.h"
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#include <Support/iterator>
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#include <Support/hash_set>
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class Instruction;
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//---------------------------------------------------------------------------
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@ -267,17 +266,26 @@ MachineOperand::InitializeReg(int _regNum, bool isCCReg)
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// a CALL (if any), and return value of a RETURN.
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//---------------------------------------------------------------------------
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class MachineInstr : public Annotable, // MachineInstrs are annotable
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public NonCopyable { // Disable copy operations
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class MachineInstr : public Annotable, // MachineInstrs are annotable
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public NonCopyable { // Disable copy operations
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MachineOpCode opCode; // the opcode
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OpCodeMask opCodeMask; // extra bits for variants of an opcode
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std::vector<MachineOperand> operands; // the operands
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std::vector<Value*> implicitRefs; // values implicitly referenced by this
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std::vector<bool> implicitIsDef; // machine instruction (eg, call args)
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std::vector<bool> implicitIsDefAndUse;
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hash_set<int> regsUsed; // all machine registers used for this
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// instruction, including regs used
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// to save values across the instr.
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struct ImplicitRef {
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Value *Val;
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bool isDef, isDefAndUse;
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ImplicitRef(Value *V, bool D, bool DU) : Val(V), isDef(D), isDefAndUse(DU){}
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};
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// implicitRefs - Values implicitly referenced by this machine instruction
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// (eg, call args)
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std::vector<ImplicitRef> implicitRefs;
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// regsUsed - all machine registers used for this instruction, including regs
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// used to save values across the instruction. This is a bitset of registers.
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std::vector<bool> regsUsed;
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public:
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/*ctor*/ MachineInstr (MachineOpCode _opCode,
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OpCodeMask _opCodeMask = 0x0);
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@ -313,7 +321,7 @@ public:
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//
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// Information about implicit operands of the instruction
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//
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unsigned getNumImplicitRefs() const{return implicitRefs.size();}
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unsigned getNumImplicitRefs() const{ return implicitRefs.size();}
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bool implicitRefIsDefined(unsigned i) const;
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bool implicitRefIsDefinedAndUsed(unsigned i) const;
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@ -324,9 +332,15 @@ public:
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//
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// Information about registers used in this instruction
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//
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const hash_set<int>& getRegsUsed () const { return regsUsed; }
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hash_set<int>& getRegsUsed () { return regsUsed; }
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const std::vector<bool> &getRegsUsed () const { return regsUsed; }
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// insertUsedReg - Add a register to the Used registers set...
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void insertUsedReg(unsigned Reg) {
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if (Reg >= regsUsed.size())
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regsUsed.resize(Reg+1);
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regsUsed[Reg] = true;
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}
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//
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// Debugging support
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//
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@ -477,41 +491,38 @@ MachineInstr::operandIsDefinedAndUsed(unsigned int i) const
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}
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inline bool
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MachineInstr::implicitRefIsDefined(unsigned int i) const
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MachineInstr::implicitRefIsDefined(unsigned i) const
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{
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assert(i < implicitIsDef.size() && "operand out of range!");
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return implicitIsDef[i];
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assert(i < implicitRefs.size() && "operand out of range!");
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return implicitRefs[i].isDef;
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}
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inline bool
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MachineInstr::implicitRefIsDefinedAndUsed(unsigned int i) const
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MachineInstr::implicitRefIsDefinedAndUsed(unsigned i) const
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{
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assert(i < implicitIsDefAndUse.size() && "operand out of range!");
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return implicitIsDefAndUse[i];
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assert(i < implicitRefs.size() && "operand out of range!");
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return implicitRefs[i].isDefAndUse;
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}
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inline const Value*
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MachineInstr::getImplicitRef(unsigned int i) const
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MachineInstr::getImplicitRef(unsigned i) const
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{
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assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
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return implicitRefs[i];
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return implicitRefs[i].Val;
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}
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inline Value*
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MachineInstr::getImplicitRef(unsigned int i)
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MachineInstr::getImplicitRef(unsigned i)
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{
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assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
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return implicitRefs[i];
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return implicitRefs[i].Val;
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}
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inline void
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MachineInstr::addImplicitRef(Value* val,
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bool isDef,
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bool isDefAndUse)
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{
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implicitRefs.push_back(val);
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implicitIsDef.push_back(isDef);
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implicitIsDefAndUse.push_back(isDefAndUse);
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bool isDefAndUse) {
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implicitRefs.push_back(ImplicitRef(val, isDef, isDefAndUse));
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}
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inline void
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@ -521,9 +532,9 @@ MachineInstr::setImplicitRef(unsigned int i,
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bool isDefAndUse)
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{
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assert(i < implicitRefs.size() && "setImplicitRef() out of range!");
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implicitRefs[i] = val;
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implicitIsDef[i] = isDef;
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implicitIsDefAndUse[i] = isDefAndUse;
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implicitRefs[i].Val = val;
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implicitRefs[i].isDef = isDef;
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implicitRefs[i].isDefAndUse = isDefAndUse;
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}
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inline void
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@ -82,14 +82,14 @@ MachineInstr::SetMachineOperandReg(unsigned int i,
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operands[i].markDef();
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if (isDefAndUse)
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operands[i].markDefAndUse();
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regsUsed.insert(regNum);
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insertUsedReg(regNum);
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}
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void
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MachineInstr::SetRegForOperand(unsigned i, int regNum)
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{
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operands[i].setRegForValue(regNum);
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regsUsed.insert(regNum);
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insertUsedReg(regNum);
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}
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@ -111,10 +111,10 @@ MachineInstr::substituteValue(const Value* oldVal, Value* newVal, bool defsOnly)
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// Subsitute implicit refs
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for (unsigned i=0, N=implicitRefs.size(); i < N; ++i)
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if (implicitRefs[i] == oldVal)
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if (getImplicitRef(i) == oldVal)
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if (!defsOnly || implicitRefIsDefined(i))
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{
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implicitRefs[i] = newVal;
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implicitRefs[i].Val = newVal;
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++numSubst;
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}
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@ -691,10 +691,10 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
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int scratchReg = -1;
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if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
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{
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scratchReg = this->getUsableUniRegAtMI(scratchRegType, &LVSetBef,
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MInst, MIBef, MIAft);
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scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
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MInst, MIBef, MIAft);
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assert(scratchReg != MRI.getInvalidRegNum());
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MInst->getRegsUsed().insert(scratchReg);
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MInst->insertUsedReg(scratchReg);
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}
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if (!isDef || isDefAndUse) {
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@ -774,7 +774,7 @@ int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
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// of copying it to memory and back. But we have to mark the
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// register as used by this instruction, so it does not get used
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// as a scratch reg. by another operand or anyone else.
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MInst->getRegsUsed().insert(scratchReg);
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MInst->insertUsedReg(scratchReg);
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MRI.cpReg2RegMI(MIBef, RegU, scratchReg, RegType);
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MRI.cpReg2RegMI(MIAft, scratchReg, RegU, RegType);
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}
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@ -874,12 +874,11 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC,
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// Add the registers already marked as used by the instruction.
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// This should include any scratch registers that are used to save
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// values across the instruction (e.g., for saving state register values).
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const hash_set<int>& regsUsed = MInst->getRegsUsed();
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for (hash_set<int>::const_iterator SI=regsUsed.begin(), SE=regsUsed.end();
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SI != SE; ++SI)
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{
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const vector<bool> ®sUsed = MInst->getRegsUsed();
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for (unsigned i = 0, e = regsUsed.size(); i != e; ++i)
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if (regsUsed[i]) {
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unsigned classId = 0;
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int classRegNum = MRI.getClassRegNum(*SI, classId);
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int classRegNum = MRI.getClassRegNum(i, classId);
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if (RC->getID() == classId)
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{
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assert(classRegNum < (int) IsColorUsedArr.size() &&
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int scratchReg = -1;
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if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
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{
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scratchReg = this->getUsableUniRegAtMI(scratchRegType, &LVSetBef,
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MInst, MIBef, MIAft);
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scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
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MInst, MIBef, MIAft);
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assert(scratchReg != MRI.getInvalidRegNum());
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MInst->getRegsUsed().insert(scratchReg);
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MInst->insertUsedReg(scratchReg);
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}
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if (!isDef || isDefAndUse) {
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@ -774,7 +774,7 @@ int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
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// of copying it to memory and back. But we have to mark the
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// register as used by this instruction, so it does not get used
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// as a scratch reg. by another operand or anyone else.
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MInst->getRegsUsed().insert(scratchReg);
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MInst->insertUsedReg(scratchReg);
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MRI.cpReg2RegMI(MIBef, RegU, scratchReg, RegType);
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MRI.cpReg2RegMI(MIAft, scratchReg, RegU, RegType);
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}
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@ -874,12 +874,11 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC,
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// Add the registers already marked as used by the instruction.
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// This should include any scratch registers that are used to save
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// values across the instruction (e.g., for saving state register values).
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const hash_set<int>& regsUsed = MInst->getRegsUsed();
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for (hash_set<int>::const_iterator SI=regsUsed.begin(), SE=regsUsed.end();
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SI != SE; ++SI)
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{
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const vector<bool> ®sUsed = MInst->getRegsUsed();
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for (unsigned i = 0, e = regsUsed.size(); i != e; ++i)
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if (regsUsed[i]) {
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unsigned classId = 0;
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int classRegNum = MRI.getClassRegNum(*SI, classId);
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int classRegNum = MRI.getClassRegNum(i, classId);
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if (RC->getID() == classId)
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{
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assert(classRegNum < (int) IsColorUsedArr.size() &&
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{
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isArgInReg = true;
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UniArgReg = (unsigned) UniArgRegOrNone;
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CallMI->getRegsUsed().insert(UniArgReg); // mark the reg as used
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CallMI->insertUsedReg(UniArgReg); // mark the reg as used
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}
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if (LR->hasColor()) {
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@ -788,7 +788,7 @@ void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI,
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UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
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// Mark the register as used by this instruction
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CallMI->getRegsUsed().insert(UniRetReg);
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CallMI->insertUsedReg(UniRetReg);
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// if the LR received the correct color, NOTHING to do
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recvCorrectColor = RetValLR->hasColor()? RetValLR->getColor() == CorrectCol
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@ -1026,7 +1026,7 @@ void UltraSparcRegInfo::colorRetValue(MachineInstr *RetMI,
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unsigned UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
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// Mark the register as used by this instruction
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RetMI->getRegsUsed().insert(UniRetReg);
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RetMI->insertUsedReg(UniRetReg);
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// if the LR received the correct color, NOTHING to do
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@ -1433,7 +1433,7 @@ UltraSparcRegInfo::insertCallerSavingCode(vector<MachineInstr*>& instrnsBefore,
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scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetBef,
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CallMI, AdIBef, AdIAft);
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assert(scratchReg != getInvalidRegNum());
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CallMI->getRegsUsed().insert(scratchReg);
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CallMI->insertUsedReg(scratchReg);
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}
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if (AdIBef.size() > 0)
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@ -1461,7 +1461,7 @@ UltraSparcRegInfo::insertCallerSavingCode(vector<MachineInstr*>& instrnsBefore,
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scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetAft,
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CallMI, AdIBef, AdIAft);
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assert(scratchReg != getInvalidRegNum());
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CallMI->getRegsUsed().insert(scratchReg);
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CallMI->insertUsedReg(scratchReg);
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}
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if (AdIBef.size() > 0)
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