6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-21 06:30:16 +00:00
Code Issues Projects Releases Wiki Activity

Add a -stress-regalloc=<N> option.

Browse Source 
This will limit all register classes to N registers in order to stress
test register allocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151379 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-02-24 18:34:20 +00:00
parent 3161039cf3
commit 27bc818eaf
1 changed files with 9 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
lib/CodeGen/RegisterClassInfo.cpp
View File

@ -18,12 +18,16 @@
#include "RegisterClassInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
cl::opt<unsigned> StressRA("stress-regalloc", cl::Hidden, cl::init(0),
cl::value_desc("N"),
cl::desc("Limit all regclasses to N registers"));
RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0)
{}
@ -99,6 +103,10 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
// CSR aliases go after the volatile registers, preserve the target's order.
std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N]);
// Register allocator stress test. Clip register class to N registers.
if (StressRA && RCI.NumRegs > StressRA)
RCI.NumRegs = StressRA;
// Check if RC is a proper sub-class.
if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)