mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 04:29:21 +00:00
rename PPC::COND_BRANCH to PPC::BCC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31834 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
df4ed6350b
commit
289c2d5f45
@ -54,7 +54,7 @@ FunctionPass *llvm::createPPCBranchSelectionPass() {
|
|||||||
///
|
///
|
||||||
static unsigned getNumBytesForInstruction(MachineInstr *MI) {
|
static unsigned getNumBytesForInstruction(MachineInstr *MI) {
|
||||||
switch (MI->getOpcode()) {
|
switch (MI->getOpcode()) {
|
||||||
case PPC::COND_BRANCH:
|
case PPC::BCC:
|
||||||
// while this will be 4 most of the time, if we emit 8 it is just a
|
// while this will be 4 most of the time, if we emit 8 it is just a
|
||||||
// minor pessimization that saves us from having to worry about
|
// minor pessimization that saves us from having to worry about
|
||||||
// keeping the offsets up to date later when we emit long branch glue.
|
// keeping the offsets up to date later when we emit long branch glue.
|
||||||
@ -116,7 +116,7 @@ bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
|
|||||||
// We may end up deleting the MachineInstr that MBBI points to, so
|
// We may end up deleting the MachineInstr that MBBI points to, so
|
||||||
// remember its opcode now so we can refer to it after calling erase()
|
// remember its opcode now so we can refer to it after calling erase()
|
||||||
unsigned ByteSize = getNumBytesForInstruction(MBBI);
|
unsigned ByteSize = getNumBytesForInstruction(MBBI);
|
||||||
if (MBBI->getOpcode() != PPC::COND_BRANCH) {
|
if (MBBI->getOpcode() != PPC::BCC) {
|
||||||
ByteCount += ByteSize;
|
ByteCount += ByteSize;
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
@ -159,7 +159,7 @@ bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
|
|||||||
MBBJ = BuildMI(*MBB, MBBI, PPC::B, 1).addMBB(DestMBB);
|
MBBJ = BuildMI(*MBB, MBBI, PPC::B, 1).addMBB(DestMBB);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Erase the psuedo COND_BRANCH instruction, and then back up the
|
// Erase the psuedo BCC instruction, and then back up the
|
||||||
// iterator so that when the for loop increments it, we end up in
|
// iterator so that when the for loop increments it, we end up in
|
||||||
// the correct place rather than iterating off the end.
|
// the correct place rather than iterating off the end.
|
||||||
MBB->erase(MBBI);
|
MBB->erase(MBBI);
|
||||||
|
@ -1007,7 +1007,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
|
|||||||
SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
|
SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
|
||||||
SDOperand Ops[] = { CondCode, getI32Imm(getPredicateForSetCC(CC)),
|
SDOperand Ops[] = { CondCode, getI32Imm(getPredicateForSetCC(CC)),
|
||||||
N->getOperand(4), N->getOperand(0) };
|
N->getOperand(4), N->getOperand(0) };
|
||||||
return CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, Ops, 4);
|
return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
|
||||||
}
|
}
|
||||||
case ISD::BRIND: {
|
case ISD::BRIND: {
|
||||||
// FIXME: Should custom lower this.
|
// FIXME: Should custom lower this.
|
||||||
|
@ -2613,7 +2613,7 @@ PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
|
|||||||
MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
|
MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
|
||||||
MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
|
MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
|
||||||
unsigned SelectPred = MI->getOperand(4).getImm();
|
unsigned SelectPred = MI->getOperand(4).getImm();
|
||||||
BuildMI(BB, PPC::COND_BRANCH, 3)
|
BuildMI(BB, PPC::BCC, 3)
|
||||||
.addReg(MI->getOperand(1).getReg()).addImm(SelectPred).addMBB(sinkMBB);
|
.addReg(MI->getOperand(1).getReg()).addImm(SelectPred).addMBB(sinkMBB);
|
||||||
MachineFunction *F = BB->getParent();
|
MachineFunction *F = BB->getParent();
|
||||||
F->getBasicBlockList().insert(It, copy0MBB);
|
F->getBasicBlockList().insert(It, copy0MBB);
|
||||||
|
@ -192,7 +192,7 @@ bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
|
|||||||
if (LastInst->getOpcode() == PPC::B) {
|
if (LastInst->getOpcode() == PPC::B) {
|
||||||
TBB = LastInst->getOperand(0).getMachineBasicBlock();
|
TBB = LastInst->getOperand(0).getMachineBasicBlock();
|
||||||
return false;
|
return false;
|
||||||
} else if (LastInst->getOpcode() == PPC::COND_BRANCH) {
|
} else if (LastInst->getOpcode() == PPC::BCC) {
|
||||||
// Block ends with fall-through condbranch.
|
// Block ends with fall-through condbranch.
|
||||||
TBB = LastInst->getOperand(2).getMachineBasicBlock();
|
TBB = LastInst->getOperand(2).getMachineBasicBlock();
|
||||||
Cond.push_back(LastInst->getOperand(0));
|
Cond.push_back(LastInst->getOperand(0));
|
||||||
@ -211,8 +211,8 @@ bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
|
|||||||
isTerminatorInstr((--I)->getOpcode()))
|
isTerminatorInstr((--I)->getOpcode()))
|
||||||
return true;
|
return true;
|
||||||
|
|
||||||
// If the block ends with PPC::B and PPC:COND_BRANCH, handle it.
|
// If the block ends with PPC::B and PPC:BCC, handle it.
|
||||||
if (SecondLastInst->getOpcode() == PPC::COND_BRANCH &&
|
if (SecondLastInst->getOpcode() == PPC::BCC &&
|
||||||
LastInst->getOpcode() == PPC::B) {
|
LastInst->getOpcode() == PPC::B) {
|
||||||
TBB = SecondLastInst->getOperand(2).getMachineBasicBlock();
|
TBB = SecondLastInst->getOperand(2).getMachineBasicBlock();
|
||||||
Cond.push_back(SecondLastInst->getOperand(0));
|
Cond.push_back(SecondLastInst->getOperand(0));
|
||||||
@ -229,7 +229,7 @@ void PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
|
|||||||
MachineBasicBlock::iterator I = MBB.end();
|
MachineBasicBlock::iterator I = MBB.end();
|
||||||
if (I == MBB.begin()) return;
|
if (I == MBB.begin()) return;
|
||||||
--I;
|
--I;
|
||||||
if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::COND_BRANCH)
|
if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
// Remove the branch.
|
// Remove the branch.
|
||||||
@ -239,7 +239,7 @@ void PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
|
|||||||
|
|
||||||
if (I == MBB.begin()) return;
|
if (I == MBB.begin()) return;
|
||||||
--I;
|
--I;
|
||||||
if (I->getOpcode() != PPC::COND_BRANCH)
|
if (I->getOpcode() != PPC::BCC)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
// Remove the branch.
|
// Remove the branch.
|
||||||
@ -259,13 +259,13 @@ void PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|||||||
if (Cond.empty()) // Unconditional branch
|
if (Cond.empty()) // Unconditional branch
|
||||||
BuildMI(&MBB, PPC::B, 1).addMBB(TBB);
|
BuildMI(&MBB, PPC::B, 1).addMBB(TBB);
|
||||||
else // Conditional branch
|
else // Conditional branch
|
||||||
BuildMI(&MBB, PPC::COND_BRANCH, 3)
|
BuildMI(&MBB, PPC::BCC, 3)
|
||||||
.addReg(Cond[0].getReg()).addImm(Cond[1].getImm()).addMBB(TBB);
|
.addReg(Cond[0].getReg()).addImm(Cond[1].getImm()).addMBB(TBB);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Two-way Conditional Branch.
|
// Two-way Conditional Branch.
|
||||||
BuildMI(&MBB, PPC::COND_BRANCH, 3)
|
BuildMI(&MBB, PPC::BCC, 3)
|
||||||
.addReg(Cond[0].getReg()).addImm(Cond[1].getImm()).addMBB(TBB);
|
.addReg(Cond[0].getReg()).addImm(Cond[1].getImm()).addMBB(TBB);
|
||||||
BuildMI(&MBB, PPC::B, 1).addMBB(FBB);
|
BuildMI(&MBB, PPC::B, 1).addMBB(FBB);
|
||||||
}
|
}
|
||||||
|
@ -352,17 +352,18 @@ let Defs = [LR] in
|
|||||||
|
|
||||||
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
|
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
|
||||||
noResults = 1, PPC970_Unit = 7 in {
|
noResults = 1, PPC970_Unit = 7 in {
|
||||||
// COND_BRANCH is formed before branch selection, it is turned into Bcc below.
|
|
||||||
// 'opc' is a 'PPC::Predicate' value.
|
|
||||||
def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst),
|
|
||||||
"${:comment} COND_BRANCH $crS, $opc, $dst",
|
|
||||||
[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>;
|
|
||||||
let isBarrier = 1 in {
|
let isBarrier = 1 in {
|
||||||
def B : IForm<18, 0, 0, (ops target:$dst),
|
def B : IForm<18, 0, 0, (ops target:$dst),
|
||||||
"b $dst", BrB,
|
"b $dst", BrB,
|
||||||
[(br bb:$dst)]>;
|
[(br bb:$dst)]>;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// BCC is formed before branch selection, it is turned into Bxx below.
|
||||||
|
// 'opc' is a 'PPC::Predicate' value.
|
||||||
|
def BCC : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst),
|
||||||
|
"${:comment} BCC $crS, $opc, $dst",
|
||||||
|
[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>;
|
||||||
|
|
||||||
def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
|
def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
|
||||||
"blt $crS, $block", BrB>;
|
"blt $crS, $block", BrB>;
|
||||||
def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
|
def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
|
||||||
|
Loading…
Reference in New Issue
Block a user