mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
implement setXX patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166459 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler
parent
8245a17a14
commit
293e5d0e0a
@ -20,6 +20,19 @@ def mem16 : Operand<i32> {
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let EncoderMethod = "getMemEncoding";
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}
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//
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// Compare a register and immediate and place result in CC
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// Implicit use of T8
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//
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// EXT-CCRR Instruction format
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//
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class FEXT_CCRXI16_ins<bits<5> _op, string asmstr,
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InstrItinClass itin>:
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FEXT_RI16<_op, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
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!strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), [], itin> {
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let isCodeGenOnly=1;
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}
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//
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// EXT-I instruction format
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//
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@ -44,6 +57,17 @@ class FEXT_I816_ins<bits<3> _func, string asmstr,
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// Assembler formats in alphabetical order.
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// Natural and pseudos are mixed together.
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//
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// Compare two registers and place result in CC
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// Implicit use of T8
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//
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// CC-RR Instruction format
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//
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class FCCRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
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FRR16<f, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), [], itin> {
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let isCodeGenOnly=1;
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}
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//
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// EXT-RI instruction format
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//
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@ -562,7 +586,36 @@ def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
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//
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def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
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//
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// Format: SLTI rx, immediate MIPS16e
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// Purpose: Set on Less Than Immediate (Extended)
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// To record the result of a less-than comparison with a constant.
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//
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def SltiCCRxImmX16: FEXT_CCRXI16_ins<0b01010, "slti", IIAlu>;
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//
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// Format: SLTIU rx, immediate MIPS16e
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// Purpose: Set on Less Than Immediate Unsigned (Extended)
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// To record the result of a less-than comparison with a constant.
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//
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def SltiuCCRxImmX16: FEXT_CCRXI16_ins<0b01011, "sltiu", IIAlu>;
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//
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// Format: SLT rx, ry MIPS16e
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// Purpose: Set on Less Than
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// To record the result of a less-than comparison.
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//
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def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>;
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def SltCCRxRy16: FCCRR16_ins<0b00010, "slt", IIAlu>;
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// Format: SLTU rx, ry MIPS16e
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// Purpose: Set on Less Than Unsigned
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// To record the result of an unsigned less-than comparison.
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//
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def SltuCCRxRy16: FCCRR16_ins<0b00011, "sltu", IIAlu>;
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//
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// Format: SRAV ry, rx MIPS16e
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// Purpose: Shift Word Right Arithmetic Variable
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@ -705,6 +758,17 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
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def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
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// setcc patterns
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class SetCC_R16<PatFrag cond_op, Instruction I>:
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Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
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(I CPU16Regs:$rx, CPU16Regs:$ry)>;
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class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
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Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
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(I CPU16Regs:$rx, imm_type:$imm16)>;
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//
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// Some branch conditional patterns are not generated by llvm at this time.
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// Some are for seemingly arbitrary reasons not used: i.e. with signed number
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@ -757,10 +821,10 @@ def: Mips16Pat
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//
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// never called because compiler transforms a >= k to a > (k-1)
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//def: Mips16Pat
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// <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
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// (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
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// >;
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def: Mips16Pat
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<(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
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(BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
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>;
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//
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// bcond-setlt
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@ -859,5 +923,118 @@ def: Mips16Pat
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(DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
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//
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// When writing C code to test setxx these patterns,
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// some will be transformed into
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// other things. So we test using C code but using -O3 and -O0
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//
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// seteq
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//
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def : Mips16Pat
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<(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
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(SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
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def : Mips16Pat
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<(seteq CPU16Regs:$lhs, 0),
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(SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
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//
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// setge
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//
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def: Mips16Pat
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<(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
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(XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
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(LiRxImmX16 1))>;
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//
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// For constants, llvm transforms this to:
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// x > (k -1) and then reverses the operands to use setlt. So this pattern
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// is not used now by the compiler. (Presumably checking that k-1 does not
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// overflow). The compiler never uses this at a the current time, due to
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// other optimizations.
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//
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//def: Mips16Pat
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// <(setge CPU16Regs:$lhs, immSExt16:$rhs),
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// (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
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// (LiRxImmX16 1))>;
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// This catches the x >= -32768 case by transforming it to x > -32769
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//
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def: Mips16Pat
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<(setgt CPU16Regs:$lhs, -32769),
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(XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
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(LiRxImmX16 1))>;
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//
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// setgt
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//
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//
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def: Mips16Pat
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<(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
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(SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
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//
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// setle
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//
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def: Mips16Pat
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<(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
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(XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
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//
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// setlt
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//
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def: SetCC_R16<setlt, SltCCRxRy16>;
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def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
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//
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// setne
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//
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def : Mips16Pat
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<(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
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(SltuCCRxRy16 (LiRxImmX16 0),
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(XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
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//
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// setuge
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//
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def: Mips16Pat
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<(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
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(XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
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(LiRxImmX16 1))>;
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// this pattern will never be used because the compiler will transform
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// x >= k to x > (k - 1) and then use SLT
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//
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//def: Mips16Pat
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// <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
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// (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
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// (LiRxImmX16 1))>;
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//
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// setugt
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//
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def: Mips16Pat
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<(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
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(SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
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//
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// setule
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//
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def: Mips16Pat
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<(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
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(XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
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//
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// setult
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//
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def: SetCC_R16<setult, SltuCCRxRy16>;
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def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
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def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
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(AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
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21
test/CodeGen/Mips/seteq.ll
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21
test/CodeGen/Mips/seteq.ll
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@ -0,0 +1,21 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@i = global i32 1, align 4
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@j = global i32 10, align 4
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@k = global i32 1, align 4
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@r1 = common global i32 0, align 4
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@r2 = common global i32 0, align 4
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define void @test() nounwind {
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entry:
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%0 = load i32* @i, align 4
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%1 = load i32* @k, align 4
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%cmp = icmp eq i32 %0, %1
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @r1, align 4
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; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
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; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
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; 16: move ${{[0-9]+}}, $t8
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ret void
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}
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24
test/CodeGen/Mips/seteqz.ll
Normal file
24
test/CodeGen/Mips/seteqz.ll
Normal file
@ -0,0 +1,24 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@i = global i32 0, align 4
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@j = global i32 99, align 4
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@r1 = common global i32 0, align 4
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@r2 = common global i32 0, align 4
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define void @test() nounwind {
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entry:
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%0 = load i32* @i, align 4
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%cmp = icmp eq i32 %0, 0
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @r1, align 4
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; 16: sltiu ${{[0-9]+}}, 1
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; 16: move ${{[0-9]+}}, $t8
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%1 = load i32* @j, align 4
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%cmp1 = icmp eq i32 %1, 99
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%conv2 = zext i1 %cmp1 to i32
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store i32 %conv2, i32* @r2, align 4
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; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
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; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
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; 16: move ${{[0-9]+}}, $t8
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ret void
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}
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27
test/CodeGen/Mips/setge.ll
Normal file
27
test/CodeGen/Mips/setge.ll
Normal file
@ -0,0 +1,27 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@j = global i32 -5, align 4
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@k = global i32 10, align 4
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@l = global i32 20, align 4
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@m = global i32 10, align 4
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@r1 = common global i32 0, align 4
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@r2 = common global i32 0, align 4
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@r3 = common global i32 0, align 4
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@.str = private unnamed_addr constant [22 x i8] c"1 = %i\0A1 = %i\0A0 = %i\0A\00", align 1
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define void @test() nounwind {
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entry:
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%0 = load i32* @k, align 4
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%1 = load i32* @j, align 4
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%cmp = icmp sge i32 %0, %1
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @r1, align 4
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; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
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; 16: move $[[REGISTER:[0-9]+]], $t8
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; 16: xor $[[REGISTER]], ${{[0-9]+}}
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%2 = load i32* @m, align 4
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%cmp1 = icmp sge i32 %0, %2
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%conv2 = zext i1 %cmp1 to i32
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store i32 %conv2, i32* @r2, align 4
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ret void
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}
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18
test/CodeGen/Mips/setgek.ll
Normal file
18
test/CodeGen/Mips/setgek.ll
Normal file
@ -0,0 +1,18 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@k = global i32 10, align 4
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@r1 = common global i32 0, align 4
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@r2 = common global i32 0, align 4
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@r3 = common global i32 0, align 4
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define void @test() nounwind {
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entry:
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%0 = load i32* @k, align 4
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%cmp = icmp sgt i32 %0, -32769
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @r1, align 4
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; 16: slti ${{[0-9]+}}, -32768
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; 16: move $[[REGISTER:[0-9]+]], $t8
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; 16: xor ${{[0-9]+}}, $[[REGISTER]]
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ret void
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}
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26
test/CodeGen/Mips/setle.ll
Normal file
26
test/CodeGen/Mips/setle.ll
Normal file
@ -0,0 +1,26 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@j = global i32 -5, align 4
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@k = global i32 10, align 4
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@l = global i32 20, align 4
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@m = global i32 10, align 4
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@r1 = common global i32 0, align 4
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@r2 = common global i32 0, align 4
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@r3 = common global i32 0, align 4
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define void @test() nounwind {
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entry:
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%0 = load i32* @j, align 4
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%1 = load i32* @k, align 4
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%cmp = icmp sle i32 %0, %1
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @r1, align 4
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; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
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; 16: move $[[REGISTER:[0-9]+]], $t8
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; 16: xor $[[REGISTER]], ${{[0-9]+}}
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%2 = load i32* @m, align 4
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%cmp1 = icmp sle i32 %2, %1
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%conv2 = zext i1 %cmp1 to i32
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store i32 %conv2, i32* @r2, align 4
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ret void
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}
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21
test/CodeGen/Mips/setlt.ll
Normal file
21
test/CodeGen/Mips/setlt.ll
Normal file
@ -0,0 +1,21 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@j = global i32 -5, align 4
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@k = global i32 10, align 4
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@l = global i32 20, align 4
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@m = global i32 10, align 4
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@r1 = common global i32 0, align 4
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@r2 = common global i32 0, align 4
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@r3 = common global i32 0, align 4
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define void @test() nounwind {
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entry:
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%0 = load i32* @j, align 4
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%1 = load i32* @k, align 4
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%cmp = icmp slt i32 %0, %1
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @r1, align 4
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; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
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; 16: move ${{[0-9]+}}, $t8
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ret void
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}
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20
test/CodeGen/Mips/setltk.ll
Normal file
20
test/CodeGen/Mips/setltk.ll
Normal file
@ -0,0 +1,20 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@j = global i32 -5, align 4
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@k = global i32 10, align 4
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@l = global i32 20, align 4
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@m = global i32 10, align 4
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@r1 = common global i32 0, align 4
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@r2 = common global i32 0, align 4
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@r3 = common global i32 0, align 4
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define void @test() nounwind {
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entry:
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%0 = load i32* @j, align 4
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%cmp = icmp slt i32 %0, 10
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%conv = zext i1 %cmp to i32
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store i32 %conv, i32* @r1, align 4
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; 16: slti $[[REGISTER:[0-9]+]], 10
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; 16: move $[[REGISTER]], $t8
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ret void
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}
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20
test/CodeGen/Mips/setne.ll
Normal file
20
test/CodeGen/Mips/setne.ll
Normal file
@ -0,0 +1,20 @@
|
||||
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
|
||||
@i = global i32 1, align 4
|
||||
@j = global i32 10, align 4
|
||||
@k = global i32 1, align 4
|
||||
@r1 = common global i32 0, align 4
|
||||
@r2 = common global i32 0, align 4
|
||||
|
||||
define void @test() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @i, align 4
|
||||
%1 = load i32* @k, align 4
|
||||
%cmp = icmp ne i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @r1, align 4
|
||||
; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}}
|
||||
; 16: sltu ${{[0-9]+}}, $[[REGISTER]]
|
||||
; 16: move ${{[0-9]+}}, $t8
|
||||
ret void
|
||||
}
|
||||
26
test/CodeGen/Mips/setuge.ll
Normal file
26
test/CodeGen/Mips/setuge.ll
Normal file
@ -0,0 +1,26 @@
|
||||
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
|
||||
@j = global i32 5, align 4
|
||||
@k = global i32 10, align 4
|
||||
@l = global i32 20, align 4
|
||||
@m = global i32 10, align 4
|
||||
@r1 = common global i32 0, align 4
|
||||
@r2 = common global i32 0, align 4
|
||||
@r3 = common global i32 0, align 4
|
||||
|
||||
define void @test() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @k, align 4
|
||||
%1 = load i32* @j, align 4
|
||||
%cmp = icmp uge i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @r1, align 4
|
||||
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: move $[[REGISTER:[0-9]+]], $t8
|
||||
; 16: xor $[[REGISTER]], ${{[0-9]+}}
|
||||
%2 = load i32* @m, align 4
|
||||
%cmp1 = icmp uge i32 %0, %2
|
||||
%conv2 = zext i1 %cmp1 to i32
|
||||
store i32 %conv2, i32* @r2, align 4
|
||||
ret void
|
||||
}
|
||||
21
test/CodeGen/Mips/setugt.ll
Normal file
21
test/CodeGen/Mips/setugt.ll
Normal file
@ -0,0 +1,21 @@
|
||||
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
|
||||
@j = global i32 5, align 4
|
||||
@k = global i32 10, align 4
|
||||
@l = global i32 20, align 4
|
||||
@m = global i32 10, align 4
|
||||
@r1 = common global i32 0, align 4
|
||||
@r2 = common global i32 0, align 4
|
||||
@r3 = common global i32 0, align 4
|
||||
|
||||
define void @test() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @k, align 4
|
||||
%1 = load i32* @j, align 4
|
||||
%cmp = icmp ugt i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @r1, align 4
|
||||
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: move ${{[0-9]+}}, $t8
|
||||
ret void
|
||||
}
|
||||
26
test/CodeGen/Mips/setule.ll
Normal file
26
test/CodeGen/Mips/setule.ll
Normal file
@ -0,0 +1,26 @@
|
||||
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
|
||||
@j = global i32 5, align 4
|
||||
@k = global i32 10, align 4
|
||||
@l = global i32 20, align 4
|
||||
@m = global i32 10, align 4
|
||||
@r1 = common global i32 0, align 4
|
||||
@r2 = common global i32 0, align 4
|
||||
@r3 = common global i32 0, align 4
|
||||
|
||||
define void @test() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @j, align 4
|
||||
%1 = load i32* @k, align 4
|
||||
%cmp = icmp ule i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @r1, align 4
|
||||
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: move $[[REGISTER:[0-9]+]], $t8
|
||||
; 16: xor $[[REGISTER]], ${{[0-9]+}}
|
||||
%2 = load i32* @m, align 4
|
||||
%cmp1 = icmp ule i32 %2, %1
|
||||
%conv2 = zext i1 %cmp1 to i32
|
||||
store i32 %conv2, i32* @r2, align 4
|
||||
ret void
|
||||
}
|
||||
21
test/CodeGen/Mips/setult.ll
Normal file
21
test/CodeGen/Mips/setult.ll
Normal file
@ -0,0 +1,21 @@
|
||||
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
|
||||
@j = global i32 5, align 4
|
||||
@k = global i32 10, align 4
|
||||
@l = global i32 20, align 4
|
||||
@m = global i32 10, align 4
|
||||
@r1 = common global i32 0, align 4
|
||||
@r2 = common global i32 0, align 4
|
||||
@r3 = common global i32 0, align 4
|
||||
|
||||
define void @test() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @j, align 4
|
||||
%1 = load i32* @k, align 4
|
||||
%cmp = icmp ult i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @r1, align 4
|
||||
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: move ${{[0-9]+}}, $t8
|
||||
ret void
|
||||
}
|
||||
20
test/CodeGen/Mips/setultk.ll
Normal file
20
test/CodeGen/Mips/setultk.ll
Normal file
@ -0,0 +1,20 @@
|
||||
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
|
||||
@j = global i32 5, align 4
|
||||
@k = global i32 10, align 4
|
||||
@l = global i32 20, align 4
|
||||
@m = global i32 10, align 4
|
||||
@r1 = common global i32 0, align 4
|
||||
@r2 = common global i32 0, align 4
|
||||
@r3 = common global i32 0, align 4
|
||||
|
||||
define void @test() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @j, align 4
|
||||
%cmp = icmp ult i32 %0, 10
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @r1, align 4
|
||||
; 16: sltiu $[[REGISTER:[0-9]+]], 10
|
||||
; 16: move $[[REGISTER]], $t8
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user