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inline the global 'getInstrOperandRegClass' function into its callers
now that TargetOperandInfo does the heavy lifting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77508 91177308-0d34-0410-b5e6-96231b3b80d8
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20a2a0aff3
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@ -488,12 +488,6 @@ public:
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virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
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};
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/// getInstrOperandRegClass - Return register class of the operand of an
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/// instruction of the specified TargetInstrDesc.
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const TargetRegisterClass*
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getInstrOperandRegClass(const TargetRegisterInfo *TRI,
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const TargetInstrDesc &II, unsigned Op);
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} // End llvm namespace
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#endif
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@ -449,8 +449,10 @@ void SchedulePostRATDList::PrescanInstruction(MachineInstr *MI) {
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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const TargetRegisterClass *NewRC =
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getInstrOperandRegClass(TRI, MI->getDesc(), i);
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const TargetRegisterClass *NewRC = 0;
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if (i < MI->getDesc().getNumOperands())
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NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI);
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// For now, only allow the register to be changed if its register
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// class is consistent across all uses.
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@ -521,8 +523,9 @@ void SchedulePostRATDList::ScanInstruction(MachineInstr *MI,
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if (Reg == 0) continue;
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if (!MO.isUse()) continue;
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const TargetRegisterClass *NewRC =
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getInstrOperandRegClass(TRI, MI->getDesc(), i);
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const TargetRegisterClass *NewRC = 0;
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if (i < MI->getDesc().getNumOperands())
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NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI);
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// For now, only allow the register to be changed if its register
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// class is consistent across all uses.
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@ -75,8 +75,9 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
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Match = false;
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if (User->isMachineOpcode()) {
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const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
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const TargetRegisterClass *RC =
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getInstrOperandRegClass(TRI, II, i+II.getNumDefs());
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const TargetRegisterClass *RC = 0;
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if (i+II.getNumDefs() < II.getNumOperands())
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RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI);
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if (!UseRC)
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UseRC = RC;
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else if (RC) {
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@ -160,7 +161,7 @@ void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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// is a vreg in the same register class, use the CopyToReg'd destination
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// register instead of creating a new vreg.
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unsigned VRBase = 0;
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const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, II, i);
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const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI);
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if (II.OpInfo[i].isOptionalDef()) {
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// Optional def must be a physical register.
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unsigned NumResults = CountResults(Node);
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@ -251,10 +252,10 @@ ScheduleDAGSDNodes::AddRegisterOperand(MachineInstr *MI, SDValue Op,
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// If the instruction requires a register in a different class, create
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// a new virtual register and copy the value into it.
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if (II) {
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const TargetRegisterClass *SrcRC =
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MRI.getRegClass(VReg);
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const TargetRegisterClass *DstRC =
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getInstrOperandRegClass(TRI, *II, IIOpNum);
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const TargetRegisterClass *SrcRC = MRI.getRegClass(VReg);
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const TargetRegisterClass *DstRC = 0;
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if (IIOpNum < II->getNumOperands())
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DstRC = II->OpInfo[IIOpNum].getRegClass(TRI);
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assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) &&
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"Don't have operand info for this instruction!");
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if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) {
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@ -619,7 +619,7 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
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// Make sure the copy destination register class fits the instruction
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// definition register class. The mismatch can happen as a result of earlier
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// extract_subreg, insert_subreg, subreg_to_reg coalescing.
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const TargetRegisterClass *RC = getInstrOperandRegClass(tri_, TID, 0);
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const TargetRegisterClass *RC = TID.OpInfo[0].getRegClass(tri_);
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if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
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if (mri_->getRegClass(DstReg) != RC)
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return false;
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@ -512,7 +512,7 @@ bool StackSlotColoring::PropagateBackward(MachineBasicBlock::iterator MII,
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TID.getOpcode() == TargetInstrInfo::SUBREG_TO_REG)
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return false;
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const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TID, i);
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const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);
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if (RC && !RC->contains(NewReg))
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return false;
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@ -576,7 +576,7 @@ bool StackSlotColoring::PropagateForward(MachineBasicBlock::iterator MII,
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TID.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)
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return false;
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const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TID, i);
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const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);
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if (RC && !RC->contains(NewReg))
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return false;
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FoundUse = true;
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@ -47,13 +47,3 @@ TargetOperandInfo::getRegClass(const TargetRegisterInfo *TRI) const {
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return TRI->getRegClass(RegClass);
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}
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/// getInstrOperandRegClass - Return register class of the operand of an
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/// instruction of the specified TargetInstrDesc.
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const TargetRegisterClass*
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llvm::getInstrOperandRegClass(const TargetRegisterInfo *TRI,
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const TargetInstrDesc &II, unsigned Op) {
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// FIXME: Should be an assert!
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if (Op >= II.getNumOperands())
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return NULL;
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return II.OpInfo[Op].getRegClass(TRI);
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}
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