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[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (Thumb encodings)

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194263 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Artyom Skrobov
2013-11-08 16:25:50 +00:00
parent c5c991bf31
commit 2b01682aa7
4 changed files with 239 additions and 3000 deletions
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167
test/MC/Disassembler/ARM/invalid-thumbv8.txt Normal file
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@@ -0,0 +1,167 @@
# RUN: not llvm-mc -disassemble %s -show-encoding -triple thumbv8 2>&1 | FileCheck %s
# Coprocessors other than CP10, CP11, CP14 and CP15 are undefined in ARMv8;
# but in ARMv7, all these instructions are valid
# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble %s | FileCheck %s --check-prefix=CHECK-V7
[0x00 0xee 0x00 0x01]
# CHECK-V7: cdp
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x00 0xee 0x00 0x01]
[0x00 0xee 0x00 0x0e]
# CHECK-V7: cdp
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x00 0xee 0x00 0x0e]
[0x00 0xee 0x00 0x0f]
# CHECK-V7: cdp
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x00 0xee 0x00 0x0f]
[0x00 0xfe 0x00 0x01]
# CHECK-V7: cdp2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x00 0xfe 0x00 0x01]
[0x00 0xfe 0x00 0x0e]
# CHECK-V7: cdp2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x00 0xfe 0x00 0x0e]
[0x00 0xfe 0x00 0x0f]
# CHECK-V7: cdp2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x00 0xfe 0x00 0x0f]
[0x00 0xee 0x10 0x01]
# CHECK-V7: mcr
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x00 0xee 0x10 0x01]
[0x00 0xfe 0x10 0x01]
# CHECK-V7: mcr2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x00 0xfe 0x10 0x01]
[0x00 0xfe 0x10 0x0e]
# CHECK-V7: mcr2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x00 0xfe 0x10 0x0e]
[0x00 0xfe 0x10 0x0f]
# CHECK-V7: mcr2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x00 0xfe 0x10 0x0f]
[0x10 0xee 0x10 0x01]
# CHECK-V7: mrc
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x10 0xee 0x10 0x01]
[0x10 0xfe 0x10 0x01]
# CHECK-V7: mrc2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x10 0xfe 0x10 0x01]
[0x10 0xfe 0x10 0x0e]
# CHECK-V7: mrc2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x10 0xfe 0x10 0x0e]
[0x10 0xfe 0x10 0x0f]
# CHECK-V7: mrc2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x10 0xfe 0x10 0x0f]
[0x40 0xec 0x00 0x01]
# CHECK-V7: mcrr
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x40 0xec 0x00 0x01]
[0x40 0xfc 0x00 0x01]
# CHECK-V7: mcrr2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x40 0xfc 0x00 0x01]
[0x40 0xfc 0x00 0x0e]
# CHECK-V7: mcrr2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x40 0xfc 0x00 0x0e]
[0x40 0xfc 0x00 0x0f]
# CHECK-V7: mcrr2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x40 0xfc 0x00 0x0f]
[0x50 0xec 0x00 0x01]
# CHECK-V7: mrrc
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x50 0xec 0x00 0x01]
[0x50 0xfc 0x00 0x0e]
# CHECK-V7: mrrc2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x50 0xfc 0x00 0x0e]
[0x50 0xfc 0x00 0x0f]
# CHECK-V7: mrrc2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x50 0xfc 0x00 0x0f]
[0x50 0xfc 0x00 0x01]
# CHECK-V7: mrrc2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x50 0xfc 0x00 0x01]
[0x80 0xec 0x00 0x01]
# CHECK-V7: stc
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x80 0xec 0x00 0x01]
[0x80 0xec 0x00 0x0f]
# CHECK-V7: stc
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x80 0xec 0x00 0x0f]
[0x80 0xfc 0x00 0x01]
# CHECK-V7: stc2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x80 0xfc 0x00 0x01]
[0x80 0xfc 0x00 0x0e]
# CHECK-V7: stc2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x80 0xfc 0x00 0x0e]
[0x80 0xfc 0x00 0x0f]
# CHECK-V7: stc2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x80 0xfc 0x00 0x0f]
[0x90 0xec 0x00 0x01]
# CHECK-V7: ldc
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x90 0xec 0x00 0x01]
[0x90 0xec 0x00 0x0f]
# CHECK-V7: ldc
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x90 0xec 0x00 0x0f]
[0x90 0xfc 0x00 0x01]
# CHECK-V7: ldc2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x90 0xfc 0x00 0x01]
[0x90 0xfc 0x00 0x0e]
# CHECK-V7: ldc2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x90 0xfc 0x00 0x0e]
[0x90 0xfc 0x00 0x0f]
# CHECK-V7: ldc2
# CHECK: invalid instruction encoding
# CHECK-NEXT: [0x90 0xfc 0x00 0x0f]

35
test/MC/Disassembler/ARM/thumb2-v8.txt
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@@ -3,3 +3,38 @@
# CHECK: sevl.w
0x50 0xbf
0xaf 0xf3 0x05 0x80
# These are the only coprocessor instructions that remain defined in ARMv8
# (The operations on p10/p11 disassemble into FP/NEON instructions)
0x00 0xee 0x10 0x0e
# CHECK: mcr p14
0x00 0xee 0x10 0x0f
# CHECK: mcr p15
0x10 0xee 0x10 0x0e
# CHECK: mrc p14
0x10 0xee 0x10 0x0f
# CHECK: mrc p15
0x40 0xec 0x00 0x0e
# CHECK: mcrr p14
0x40 0xec 0x00 0x0f
# CHECK: mcrr p15
0x50 0xec 0x00 0x0e
# CHECK: mrrc p14
0x50 0xec 0x00 0x0f
# CHECK: mrrc p15
0x80 0xec 0x00 0x0e
# CHECK: stc p14
0x90 0xec 0x00 0x0e
# CHECK: ldc p14