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Convert regclass alignment from bytes to bites

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15972 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-08-21 20:13:09 +00:00
parent 0e362770d0
commit 2b0e300342
1 changed files with 1 additions and 1 deletions
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lib/Target/SparcV9/SparcV9RegisterInfo.td
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@ -35,7 +35,7 @@ let Namespace = "SparcV9" in {
// FIXME: the register order should be defined in terms of the preferred
// allocation order...
//
def IntRegs : RegisterClass<i64, 8, [G0, G1, G2, G3, G4, G5, G6, G7,
def IntRegs : RegisterClass<i64, 64, [G0, G1, G2, G3, G4, G5, G6, G7,
O0, O1, O2, O3, O4, O5, O6, O7,
L0, L1, L2, L3, L4, L5, L6, L7,
I0, I1, I2, I3, I4, I5, I6, I7]>;