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Fix invalid for vector types fneg(bitconvert(x)) => bitconvert(x ^ sign)

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transform.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84683 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2009-10-20 21:37:45 +00:00
parent 3fd7a68ba9
commit 2bcf60a9cc
2 changed files with 54 additions and 4 deletions
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10
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -4381,15 +4381,17 @@ SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
SDValue DAGCombiner::visitFNEG(SDNode *N) {
SDValue N0 = N->getOperand(0);
EVT VT = N->getValueType(0);
if (isNegatibleForFree(N0, LegalOperations))
return GetNegatedExpression(N0, DAG, LegalOperations);
// Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
// constant pool values.
if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
N0.getOperand(0).getValueType().isInteger() &&
!N0.getOperand(0).getValueType().isVector()) {
if (N0.getOpcode() == ISD::BIT_CONVERT &&
!VT.isVector() &&
N0.getNode()->hasOneUse() &&
N0.getOperand(0).getValueType().isInteger()) {
SDValue Int = N0.getOperand(0);
EVT IntVT = Int.getValueType();
if (IntVT.isInteger() && !IntVT.isVector()) {
@ -4397,7 +4399,7 @@ SDValue DAGCombiner::visitFNEG(SDNode *N) {
DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
AddToWorkList(Int.getNode());
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
N->getValueType(0), Int);
VT, Int);
}
}

48
test/CodeGen/ARM/2009-10-21-InvalidFNeg.ll Normal file
View File

@ -0,0 +1,48 @@
; RUN: llc -mcpu=cortex-a8 -mattr=+neon < %s | grep vneg
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "armv7-eabi"
%aaa = type { %fff, %fff }
%bbb = type { [6 x %ddd] }
%ccc = type { %eee, %fff }
%ddd = type { %fff }
%eee = type { %fff, %fff, %fff, %fff }
%fff = type { %struct.vec_float4 }
%struct.vec_float4 = type { <4 x float> }
define linkonce_odr arm_aapcs_vfpcc void @foo(%eee* noalias sret %agg.result, i64 %tfrm.0.0, i64 %tfrm.0.1, i64 %tfrm.0.2, i64 %tfrm.0.3, i64 %tfrm.0.4, i64 %tfrm.0.5, i64 %tfrm.0.6, i64 %tfrm.0.7) nounwind noinline {
entry:
%tmp104 = zext i64 %tfrm.0.2 to i512 ; <i512> [#uses=1]
%tmp105 = shl i512 %tmp104, 128 ; <i512> [#uses=1]
%tmp118 = zext i64 %tfrm.0.3 to i512 ; <i512> [#uses=1]
%tmp119 = shl i512 %tmp118, 192 ; <i512> [#uses=1]
%ins121 = or i512 %tmp119, %tmp105 ; <i512> [#uses=1]
%tmp99 = zext i64 %tfrm.0.4 to i512 ; <i512> [#uses=1]
%tmp100 = shl i512 %tmp99, 256 ; <i512> [#uses=1]
%tmp123 = zext i64 %tfrm.0.5 to i512 ; <i512> [#uses=1]
%tmp124 = shl i512 %tmp123, 320 ; <i512> [#uses=1]
%tmp96 = zext i64 %tfrm.0.6 to i512 ; <i512> [#uses=1]
%tmp97 = shl i512 %tmp96, 384 ; <i512> [#uses=1]
%tmp128 = zext i64 %tfrm.0.7 to i512 ; <i512> [#uses=1]
%tmp129 = shl i512 %tmp128, 448 ; <i512> [#uses=1]
%mask.masked = or i512 %tmp124, %tmp100 ; <i512> [#uses=1]
%ins131 = or i512 %tmp129, %tmp97 ; <i512> [#uses=1]
%tmp109132 = zext i64 %tfrm.0.0 to i128 ; <i128> [#uses=1]
%tmp113134 = zext i64 %tfrm.0.1 to i128 ; <i128> [#uses=1]
%tmp114133 = shl i128 %tmp113134, 64 ; <i128> [#uses=1]
%tmp94 = or i128 %tmp114133, %tmp109132 ; <i128> [#uses=1]
%tmp95 = bitcast i128 %tmp94 to <4 x float> ; <<4 x float>> [#uses=0]
%tmp82 = lshr i512 %ins121, 128 ; <i512> [#uses=1]
%tmp83 = trunc i512 %tmp82 to i128 ; <i128> [#uses=1]
%tmp84 = bitcast i128 %tmp83 to <4 x float> ; <<4 x float>> [#uses=0]
%tmp86 = lshr i512 %mask.masked, 256 ; <i512> [#uses=1]
%tmp87 = trunc i512 %tmp86 to i128 ; <i128> [#uses=1]
%tmp88 = bitcast i128 %tmp87 to <4 x float> ; <<4 x float>> [#uses=0]
%tmp90 = lshr i512 %ins131, 384 ; <i512> [#uses=1]
%tmp91 = trunc i512 %tmp90 to i128 ; <i128> [#uses=1]
%tmp92 = bitcast i128 %tmp91 to <4 x float> ; <<4 x float>> [#uses=1]
%tmp = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %tmp92 ; <<4 x float>> [#uses=1]
%tmp28 = getelementptr inbounds %eee* %agg.result, i32 0, i32 3, i32 0, i32 0 ; <<4 x float>*> [#uses=1]
store <4 x float> %tmp, <4 x float>* %tmp28, align 16
ret void
}