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Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137061 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -977,7 +977,8 @@ multiclass T2I_st<bits<2> opcod, string opc,
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class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
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: T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
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opc, ".w\t$Rd, $Rm$rot",
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[(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> {
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[(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
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Requires<[IsThumb2]> {
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let Inst{31-27} = 0b11111;
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let Inst{26-23} = 0b0100;
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let Inst{22-20} = opcod;
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@ -3407,9 +3408,9 @@ def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
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// SXT/UXT with no rotate
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let AddedComplexity = 16 in {
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def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
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Requires<[HasT2ExtractPack, IsThumb2]>;
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Requires<[IsThumb2]>;
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def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
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Requires<[HasT2ExtractPack, IsThumb2]>;
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Requires<[IsThumb2]>;
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def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
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Requires<[HasT2ExtractPack, IsThumb2]>;
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def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
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@ -3421,9 +3422,9 @@ def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
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}
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def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>,
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Requires<[HasT2ExtractPack, IsThumb2]>;
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Requires<[IsThumb2]>;
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def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
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Requires<[HasT2ExtractPack, IsThumb2]>;
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Requires<[IsThumb2]>;
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def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
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(t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
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Requires<[HasT2ExtractPack, IsThumb2]>;
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29
test/CodeGen/Thumb2/thumb2-sxt-uxt.ll
Normal file
29
test/CodeGen/Thumb2/thumb2-sxt-uxt.ll
Normal file
@ -0,0 +1,29 @@
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; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s
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define i32 @test1(i16 zeroext %z) nounwind {
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; CHECK: test1:
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; CHECK: sxth
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%r = sext i16 %z to i32
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ret i32 %r
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}
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define i32 @test2(i8 zeroext %z) nounwind {
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; CHECK: test2:
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; CHECK: sxtb
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%r = sext i8 %z to i32
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ret i32 %r
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}
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define i32 @test3(i16 signext %z) nounwind {
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; CHECK: test3:
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; CHECK: uxth
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%r = zext i16 %z to i32
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ret i32 %r
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}
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define i32 @test4(i8 signext %z) nounwind {
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; CHECK: test4:
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; CHECK: uxtb
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%r = zext i8 %z to i32
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ret i32 %r
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}
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