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[MIPS] Move MIPS ABI flags structure constants to the separate header

Browse Source 
http://reviews.llvm.org/D9517

The separate header file allows to reuse the MIPS ABI flags structure
constants in other LLVM tools like the llvm-readobj.

No functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236732 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Atanasyan 2015-05-07 14:57:04 +00:00
parent f6fa999df3
commit 2d0087d82a
3 changed files with 128 additions and 84 deletions
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102
include/llvm/Support/MipsABIFlags.h Normal file
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@ -0,0 +1,102 @@
//===--- MipsABIFlags.h - MIPS ABI flags ----------------------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the constants for the ABI flags structure contained
// in the .MIPS.abiflags section.
//
// https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_SUPPORT_MIPSABIFLAGS_H
#define LLVM_SUPPORT_MIPSABIFLAGS_H
namespace llvm {
namespace Mips {
// Values for the xxx_size bytes of an ABI flags structure.
enum AFL_REG {
AFL_REG_NONE = 0x00, // No registers
AFL_REG_32 = 0x01, // 32-bit registers
AFL_REG_64 = 0x02, // 64-bit registers
AFL_REG_128 = 0x03 // 128-bit registers
};
// Masks for the ases word of an ABI flags structure.
enum AFL_ASE {
AFL_ASE_DSP = 0x00000001, // DSP ASE
AFL_ASE_DSPR2 = 0x00000002, // DSP R2 ASE
AFL_ASE_EVA = 0x00000004, // Enhanced VA Scheme
AFL_ASE_MCU = 0x00000008, // MCU (MicroController) ASE
AFL_ASE_MDMX = 0x00000010, // MDMX ASE
AFL_ASE_MIPS3D = 0x00000020, // MIPS-3D ASE
AFL_ASE_MT = 0x00000040, // MT ASE
AFL_ASE_SMARTMIPS = 0x00000080, // SmartMIPS ASE
AFL_ASE_VIRT = 0x00000100, // VZ ASE
AFL_ASE_MSA = 0x00000200, // MSA ASE
AFL_ASE_MIPS16 = 0x00000400, // MIPS16 ASE
AFL_ASE_MICROMIPS = 0x00000800, // MICROMIPS ASE
AFL_ASE_XPA = 0x00001000 // XPA ASE
};
// Values for the isa_ext word of an ABI flags structure.
enum AFL_EXT {
AFL_EXT_NONE = 0, // None
AFL_EXT_XLR = 1, // RMI Xlr instruction
AFL_EXT_OCTEON2 = 2, // Cavium Networks Octeon2
AFL_EXT_OCTEONP = 3, // Cavium Networks OcteonP
AFL_EXT_LOONGSON_3A = 4, // Loongson 3A
AFL_EXT_OCTEON = 5, // Cavium Networks Octeon
AFL_EXT_5900 = 6, // MIPS R5900 instruction
AFL_EXT_4650 = 7, // MIPS R4650 instruction
AFL_EXT_4010 = 8, // LSI R4010 instruction
AFL_EXT_4100 = 9, // NEC VR4100 instruction
AFL_EXT_3900 = 10, // Toshiba R3900 instruction
AFL_EXT_10000 = 11, // MIPS R10000 instruction
AFL_EXT_SB1 = 12, // Broadcom SB-1 instruction
AFL_EXT_4111 = 13, // NEC VR4111/VR4181 instruction
AFL_EXT_4120 = 14, // NEC VR4120 instruction
AFL_EXT_5400 = 15, // NEC VR5400 instruction
AFL_EXT_5500 = 16, // NEC VR5500 instruction
AFL_EXT_LOONGSON_2E = 17, // ST Microelectronics Loongson 2E
AFL_EXT_LOONGSON_2F = 18, // ST Microelectronics Loongson 2F
AFL_EXT_OCTEON3 = 19 // Cavium Networks Octeon3
};
// Values for the flags1 word of an ABI flags structure.
enum AFL_FLAGS1 { AFL_FLAGS1_ODDSPREG = 1 };
// MIPS object attribute tags
enum {
Tag_GNU_MIPS_ABI_FP = 4, // Floating-point ABI used by this object file
Tag_GNU_MIPS_ABI_MSA = 8, // MSA ABI used by this object file
};
// Values for the fp_abi word of an ABI flags structure
// and for the Tag_GNU_MIPS_ABI_FP attribute tag.
enum Val_GNU_MIPS_ABI_FP {
Val_GNU_MIPS_ABI_FP_ANY = 0, // not tagged
Val_GNU_MIPS_ABI_FP_DOUBLE = 1, // hard float / -mdouble-float
Val_GNU_MIPS_ABI_FP_SINGLE = 2, // hard float / -msingle-float
Val_GNU_MIPS_ABI_FP_SOFT = 3, // soft float
Val_GNU_MIPS_ABI_FP_OLD_64 = 4, // -mips32r2 -mfp64
Val_GNU_MIPS_ABI_FP_XX = 5, // -mfpxx
Val_GNU_MIPS_ABI_FP_64 = 6, // -mips32r2 -mfp64
Val_GNU_MIPS_ABI_FP_64A = 7 // -mips32r2 -mfp64 -mno-odd-spreg
};
// Values for the Tag_GNU_MIPS_ABI_MSA attribute tag.
enum Val_GNU_MIPS_ABI_MSA {
Val_GNU_MIPS_ABI_MSA_ANY = 0, // not tagged
Val_GNU_MIPS_ABI_MSA_128 = 1 // 128-bit MSA
};
}
}
#endif

15
lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp
View File

@ -14,17 +14,18 @@ using namespace llvm;
uint8_t MipsABIFlagsSection::getFpABIValue() {
switch (FpABI) {
case FpABIKind::ANY:
return Val_GNU_MIPS_ABI_FP_ANY;
return Mips::Val_GNU_MIPS_ABI_FP_ANY;
case FpABIKind::SOFT:
return Val_GNU_MIPS_ABI_FP_SOFT;
return Mips::Val_GNU_MIPS_ABI_FP_SOFT;
case FpABIKind::XX:
return Val_GNU_MIPS_ABI_FP_XX;
return Mips::Val_GNU_MIPS_ABI_FP_XX;
case FpABIKind::S32:
return Val_GNU_MIPS_ABI_FP_DOUBLE;
return Mips::Val_GNU_MIPS_ABI_FP_DOUBLE;
case FpABIKind::S64:
if (Is32BitABI)
return OddSPReg ? Val_GNU_MIPS_ABI_FP_64 : Val_GNU_MIPS_ABI_FP_64A;
return Val_GNU_MIPS_ABI_FP_DOUBLE;
return OddSPReg ? Mips::Val_GNU_MIPS_ABI_FP_64
: Mips::Val_GNU_MIPS_ABI_FP_64A;
return Mips::Val_GNU_MIPS_ABI_FP_DOUBLE;
}
llvm_unreachable("unexpected fp abi value");
@ -45,7 +46,7 @@ StringRef MipsABIFlagsSection::getFpABIString(FpABIKind Value) {
uint8_t MipsABIFlagsSection::getCPR1SizeValue() {
if (FpABI == FpABIKind::XX)
return (uint8_t)AFL_REG_32;
return (uint8_t)Mips::AFL_REG_32;
return (uint8_t)CPR1Size;
}

95
lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h
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@ -11,73 +11,13 @@
#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIFLAGSSECTION_H
#include "llvm/MC/MCStreamer.h"
#include "llvm/Support/MipsABIFlags.h"
namespace llvm {
class MCStreamer;
struct MipsABIFlagsSection {
// Values for the xxx_size bytes of an ABI flags structure.
enum AFL_REG {
AFL_REG_NONE = 0x00, // No registers.
AFL_REG_32 = 0x01, // 32-bit registers.
AFL_REG_64 = 0x02, // 64-bit registers.
AFL_REG_128 = 0x03 // 128-bit registers.
};
// Masks for the ases word of an ABI flags structure.
enum AFL_ASE {
AFL_ASE_DSP = 0x00000001, // DSP ASE.
AFL_ASE_DSPR2 = 0x00000002, // DSP R2 ASE.
AFL_ASE_EVA = 0x00000004, // Enhanced VA Scheme.
AFL_ASE_MCU = 0x00000008, // MCU (MicroController) ASE.
AFL_ASE_MDMX = 0x00000010, // MDMX ASE.
AFL_ASE_MIPS3D = 0x00000020, // MIPS-3D ASE.
AFL_ASE_MT = 0x00000040, // MT ASE.
AFL_ASE_SMARTMIPS = 0x00000080, // SmartMIPS ASE.
AFL_ASE_VIRT = 0x00000100, // VZ ASE.
AFL_ASE_MSA = 0x00000200, // MSA ASE.
AFL_ASE_MIPS16 = 0x00000400, // MIPS16 ASE.
AFL_ASE_MICROMIPS = 0x00000800, // MICROMIPS ASE.
AFL_ASE_XPA = 0x00001000 // XPA ASE.
};
// Values for the isa_ext word of an ABI flags structure.
enum AFL_EXT {
AFL_EXT_XLR = 1, // RMI Xlr instruction.
AFL_EXT_OCTEON2 = 2, // Cavium Networks Octeon2.
AFL_EXT_OCTEONP = 3, // Cavium Networks OcteonP.
AFL_EXT_LOONGSON_3A = 4, // Loongson 3A.
AFL_EXT_OCTEON = 5, // Cavium Networks Octeon.
AFL_EXT_5900 = 6, // MIPS R5900 instruction.
AFL_EXT_4650 = 7, // MIPS R4650 instruction.
AFL_EXT_4010 = 8, // LSI R4010 instruction.
AFL_EXT_4100 = 9, // NEC VR4100 instruction.
AFL_EXT_3900 = 10, // Toshiba R3900 instruction.
AFL_EXT_10000 = 11, // MIPS R10000 instruction.
AFL_EXT_SB1 = 12, // Broadcom SB-1 instruction.
AFL_EXT_4111 = 13, // NEC VR4111/VR4181 instruction.
AFL_EXT_4120 = 14, // NEC VR4120 instruction.
AFL_EXT_5400 = 15, // NEC VR5400 instruction.
AFL_EXT_5500 = 16, // NEC VR5500 instruction.
AFL_EXT_LOONGSON_2E = 17, // ST Microelectronics Loongson 2E.
AFL_EXT_LOONGSON_2F = 18 // ST Microelectronics Loongson 2F.
};
// Values for the fp_abi word of an ABI flags structure.
enum Val_GNU_MIPS_ABI {
Val_GNU_MIPS_ABI_FP_ANY = 0,
Val_GNU_MIPS_ABI_FP_DOUBLE = 1,
Val_GNU_MIPS_ABI_FP_SOFT = 3,
Val_GNU_MIPS_ABI_FP_XX = 5,
Val_GNU_MIPS_ABI_FP_64 = 6,
Val_GNU_MIPS_ABI_FP_64A = 7
};
enum AFL_FLAGS1 {
AFL_FLAGS1_ODDSPREG = 1
};
// Internal representation of the fp_abi related values used in .module.
enum class FpABIKind { ANY, XX, S32, S64, SOFT };
@ -88,11 +28,11 @@ struct MipsABIFlagsSection {
// The revision of ISA: 0 for MIPS V and below, 1-n otherwise.
uint8_t ISARevision;
// The size of general purpose registers.
AFL_REG GPRSize;
Mips::AFL_REG GPRSize;
// The size of co-processor 1 registers.
AFL_REG CPR1Size;
Mips::AFL_REG CPR1Size;
// The size of co-processor 2 registers.
AFL_REG CPR2Size;
Mips::AFL_REG CPR2Size;
// Processor-specific extension.
uint32_t ISAExtensionSet;
// Mask of ASEs used.
@ -108,9 +48,10 @@ protected:
public:
MipsABIFlagsSection()
: Version(0), ISALevel(0), ISARevision(0), GPRSize(AFL_REG_NONE),
CPR1Size(AFL_REG_NONE), CPR2Size(AFL_REG_NONE), ISAExtensionSet(0),
ASESet(0), OddSPReg(false), Is32BitABI(false), FpABI(FpABIKind::ANY) {}
: Version(0), ISALevel(0), ISARevision(0), GPRSize(Mips::AFL_REG_NONE),
CPR1Size(Mips::AFL_REG_NONE), CPR2Size(Mips::AFL_REG_NONE),
ISAExtensionSet(0), ASESet(0), OddSPReg(false), Is32BitABI(false),
FpABI(FpABIKind::ANY) {}
uint16_t getVersionValue() { return (uint16_t)Version; }
uint8_t getISALevelValue() { return (uint8_t)ISALevel; }
@ -126,7 +67,7 @@ public:
uint32_t Value = 0;
if (OddSPReg)
Value |= (uint32_t)AFL_FLAGS1_ODDSPREG;
Value |= (uint32_t)Mips::AFL_FLAGS1_ODDSPREG;
return Value;
}
@ -185,32 +126,32 @@ public:
template <class PredicateLibrary>
void setGPRSizeFromPredicates(const PredicateLibrary &P) {
GPRSize = P.isGP64bit() ? AFL_REG_64 : AFL_REG_32;
GPRSize = P.isGP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32;
}
template <class PredicateLibrary>
void setCPR1SizeFromPredicates(const PredicateLibrary &P) {
if (P.abiUsesSoftFloat())
CPR1Size = AFL_REG_NONE;
CPR1Size = Mips::AFL_REG_NONE;
else if (P.hasMSA())
CPR1Size = AFL_REG_128;
CPR1Size = Mips::AFL_REG_128;
else
CPR1Size = P.isFP64bit() ? AFL_REG_64 : AFL_REG_32;
CPR1Size = P.isFP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32;
}
template <class PredicateLibrary>
void setASESetFromPredicates(const PredicateLibrary &P) {
ASESet = 0;
if (P.hasDSP())
ASESet |= AFL_ASE_DSP;
ASESet |= Mips::AFL_ASE_DSP;
if (P.hasDSPR2())
ASESet |= AFL_ASE_DSPR2;
ASESet |= Mips::AFL_ASE_DSPR2;
if (P.hasMSA())
ASESet |= AFL_ASE_MSA;
ASESet |= Mips::AFL_ASE_MSA;
if (P.inMicroMipsMode())
ASESet |= AFL_ASE_MICROMIPS;
ASESet |= Mips::AFL_ASE_MICROMIPS;
if (P.inMips16Mode())
ASESet |= AFL_ASE_MIPS16;
ASESet |= Mips::AFL_ASE_MIPS16;
}
template <class PredicateLibrary>