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Factor out dbg_value comment printing and teach MC asm printing to use it.
This should make the arm-linux self-host buildbot happy again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114964 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -212,6 +212,8 @@ namespace {
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void EmitStartOfAsmFile(Module &M);
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void EmitEndOfAsmFile(Module &M);
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void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
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MachineLocation getDebugValueLocation(const MachineInstr *MI) const {
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MachineLocation Location;
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assert (MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
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@ -1146,19 +1148,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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if (MI->getOpcode() == ARM::DBG_VALUE) {
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unsigned NOps = MI->getNumOperands();
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assert(NOps==4);
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OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
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// cast away const; DIetc do not take const operands for some reason.
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DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
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OS << V.getName();
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OS << " <- ";
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// Frame address. Currently handles register +- offset only.
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assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
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OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
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OS << ']';
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OS << "+";
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printOperand(MI, NOps-2, OS);
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PrintDebugValueComment(MI, OS);
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} else if (MI->getOpcode() == ARM::MOVs) {
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// FIXME: Thumb variants?
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const MachineOperand &Dst = MI->getOperand(0);
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@ -1503,12 +1493,38 @@ void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
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EmitAlignment(1);
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}
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void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
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raw_ostream &OS) {
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unsigned NOps = MI->getNumOperands();
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assert(NOps==4);
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OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
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// cast away const; DIetc do not take const operands for some reason.
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DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
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OS << V.getName();
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OS << " <- ";
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// Frame address. Currently handles register +- offset only.
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assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
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OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
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OS << ']';
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OS << "+";
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printOperand(MI, NOps-2, OS);
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}
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void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
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ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
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switch (MI->getOpcode()) {
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case ARM::t2MOVi32imm:
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assert(0 && "Should be lowered by thumb2it pass");
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default: break;
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case ARM::DBG_VALUE: {
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if (isVerbose() && OutStreamer.hasRawTextSupport()) {
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SmallString<128> TmpStr;
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raw_svector_ostream OS(TmpStr);
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PrintDebugValueComment(MI, OS);
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OutStreamer.EmitRawText(StringRef(OS.str()));
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}
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return;
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}
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case ARM::tPICADD: {
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// This is a pseudo op for a label + instruction sequence, which looks like:
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// LPC0:
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