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Custom lower f64 args passed in integer registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116977 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1356,6 +1356,21 @@ bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
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VA.getLocReg())
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VA.getLocReg())
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.addReg(Arg);
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.addReg(Arg);
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RegArgs.push_back(VA.getLocReg());
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RegArgs.push_back(VA.getLocReg());
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} else if (VA.needsCustom()) {
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// TODO: We need custom lowering for vector (v2f64) args.
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if (VA.getLocVT() != MVT::f64) return false;
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CCValAssign &NextVA = ArgLocs[++i];
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// TODO: Only handle register args for now.
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if(!(VA.isRegLoc() && NextVA.isRegLoc())) return false;
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(ARM::VMOVRRD), VA.getLocReg())
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.addReg(NextVA.getLocReg(), RegState::Define)
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.addReg(Arg));
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RegArgs.push_back(VA.getLocReg());
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RegArgs.push_back(NextVA.getLocReg());
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} else {
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} else {
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// Need to store
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// Need to store
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return false;
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return false;
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