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Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters)

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159938 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Barton
2012-07-09 16:41:33 +00:00
parent 8ed97ef5f6
commit 2e7e34ba54
3 changed files with 29 additions and 8 deletions
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8
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -4198,9 +4198,9 @@ static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
DecodeStatus S = MCDisassembler::Success;
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
unsigned Rm = fieldFromInstruction32(Insn, 5, 1);
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
Rm |= fieldFromInstruction32(Insn, 0, 4) << 4;
if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
S = MCDisassembler::SoftFail;
@ -4224,9 +4224,9 @@ static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
DecodeStatus S = MCDisassembler::Success;
unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
unsigned Rm = fieldFromInstruction32(Insn, 5, 1);
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
Rm |= fieldFromInstruction32(Insn, 0, 4) << 4;
if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
S = MCDisassembler::SoftFail;