6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-14 00:32:55 +00:00
Code Issues Projects Releases Wiki Activity

[PowerPC] Add predicted forms of branches

Browse Source 
This adds support for the predicted forms of branches (+/-).
There are three cases to consider:
- Branches using a PPC::Predicate code
  For these, I've added new PPC::Predicate codes corresponding
  to the BO values for predicted branch forms, and updated insn
  printing to print them correctly.  I've also added new aliases
  for the asm parser matching the new forms.
- bt/bf
  I've added new aliases matching to gBC etc.
- bd(n)z variants
  I've added new instruction patterns for the predicted forms.

In all cases, the new patterns are used for the asm parser only.
(The new infrastructure ought to be sufficient to allow use by
the compiler too at some point.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184754 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ulrich Weigand 2013-06-24 16:52:04 +00:00
parent a6a3fd6415
commit 2e8bd89503
7 changed files with 1392 additions and 65 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
View File

@ -747,6 +747,22 @@ bool PPCAsmParser::
ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// The first operand is the token for the instruction name.
// If the next character is a '+' or '-', we need to add it to the
// instruction name, to match what TableGen is doing.
if (getLexer().is(AsmToken::Plus)) {
getLexer().Lex();
char *NewOpcode = new char[Name.size() + 1];
memcpy(NewOpcode, Name.data(), Name.size());
NewOpcode[Name.size()] = '+';
Name = StringRef(NewOpcode, Name.size() + 1);
}
if (getLexer().is(AsmToken::Minus)) {
getLexer().Lex();
char *NewOpcode = new char[Name.size() + 1];
memcpy(NewOpcode, Name.data(), Name.size());
NewOpcode[Name.size()] = '-';
Name = StringRef(NewOpcode, Name.size() + 1);
}
// If the instruction ends in a '.', we need to create a separate
// token for it, to match what TableGen is doing.
size_t Dot = Name.find('.');

88
lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
View File

@ -90,19 +90,89 @@ void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
if (StringRef(Modifier) == "cc") {
switch ((PPC::Predicate)Code) {
case PPC::PRED_LT: O << "lt"; return;
case PPC::PRED_LE: O << "le"; return;
case PPC::PRED_EQ: O << "eq"; return;
case PPC::PRED_GE: O << "ge"; return;
case PPC::PRED_GT: O << "gt"; return;
case PPC::PRED_NE: O << "ne"; return;
case PPC::PRED_UN: O << "un"; return;
case PPC::PRED_NU: O << "nu"; return;
case PPC::PRED_LT_MINUS:
case PPC::PRED_LT_PLUS:
case PPC::PRED_LT:
O << "lt";
return;
case PPC::PRED_LE_MINUS:
case PPC::PRED_LE_PLUS:
case PPC::PRED_LE:
O << "le";
return;
case PPC::PRED_EQ_MINUS:
case PPC::PRED_EQ_PLUS:
case PPC::PRED_EQ:
O << "eq";
return;
case PPC::PRED_GE_MINUS:
case PPC::PRED_GE_PLUS:
case PPC::PRED_GE:
O << "ge";
return;
case PPC::PRED_GT_MINUS:
case PPC::PRED_GT_PLUS:
case PPC::PRED_GT:
O << "gt";
return;
case PPC::PRED_NE_MINUS:
case PPC::PRED_NE_PLUS:
case PPC::PRED_NE:
O << "ne";
return;
case PPC::PRED_UN_MINUS:
case PPC::PRED_UN_PLUS:
case PPC::PRED_UN:
O << "un";
return;
case PPC::PRED_NU_MINUS:
case PPC::PRED_NU_PLUS:
case PPC::PRED_NU:
O << "nu";
return;
default:
llvm_unreachable("Invalid predicate code");
}
}
if (StringRef(Modifier) == "pm") {
switch ((PPC::Predicate)Code) {
case PPC::PRED_LT:
case PPC::PRED_LE:
case PPC::PRED_EQ:
case PPC::PRED_GE:
case PPC::PRED_GT:
case PPC::PRED_NE:
case PPC::PRED_UN:
case PPC::PRED_NU:
return;
case PPC::PRED_LT_MINUS:
case PPC::PRED_LE_MINUS:
case PPC::PRED_EQ_MINUS:
case PPC::PRED_GE_MINUS:
case PPC::PRED_GT_MINUS:
case PPC::PRED_NE_MINUS:
case PPC::PRED_UN_MINUS:
case PPC::PRED_NU_MINUS:
O << "-";
return;
case PPC::PRED_LT_PLUS:
case PPC::PRED_LE_PLUS:
case PPC::PRED_EQ_PLUS:
case PPC::PRED_GE_PLUS:
case PPC::PRED_GT_PLUS:
case PPC::PRED_NE_PLUS:
case PPC::PRED_UN_PLUS:
case PPC::PRED_NU_PLUS:
O << "+";
return;
default:
llvm_unreachable("Invalid predicate code");
}
}
assert(StringRef(Modifier) == "reg" &&
"Need to specify 'cc' or 'reg' as predicate op modifier!");
"Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
printOperand(MI, OpNo+1, O);
}

32
lib/Target/PowerPC/MCTargetDesc/PPCPredicates.cpp
View File

@ -26,6 +26,22 @@ PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) {
case PPC::PRED_LE: return PPC::PRED_GT;
case PPC::PRED_NU: return PPC::PRED_UN;
case PPC::PRED_UN: return PPC::PRED_NU;
case PPC::PRED_EQ_MINUS: return PPC::PRED_NE_PLUS;
case PPC::PRED_NE_MINUS: return PPC::PRED_EQ_PLUS;
case PPC::PRED_LT_MINUS: return PPC::PRED_GE_PLUS;
case PPC::PRED_GE_MINUS: return PPC::PRED_LT_PLUS;
case PPC::PRED_GT_MINUS: return PPC::PRED_LE_PLUS;
case PPC::PRED_LE_MINUS: return PPC::PRED_GT_PLUS;
case PPC::PRED_NU_MINUS: return PPC::PRED_UN_PLUS;
case PPC::PRED_UN_MINUS: return PPC::PRED_NU_PLUS;
case PPC::PRED_EQ_PLUS: return PPC::PRED_NE_MINUS;
case PPC::PRED_NE_PLUS: return PPC::PRED_EQ_MINUS;
case PPC::PRED_LT_PLUS: return PPC::PRED_GE_MINUS;
case PPC::PRED_GE_PLUS: return PPC::PRED_LT_MINUS;
case PPC::PRED_GT_PLUS: return PPC::PRED_LE_MINUS;
case PPC::PRED_LE_PLUS: return PPC::PRED_GT_MINUS;
case PPC::PRED_NU_PLUS: return PPC::PRED_UN_MINUS;
case PPC::PRED_UN_PLUS: return PPC::PRED_NU_MINUS;
}
llvm_unreachable("Unknown PPC branch opcode!");
}
@ -40,6 +56,22 @@ PPC::Predicate PPC::getSwappedPredicate(PPC::Predicate Opcode) {
case PPC::PRED_LE: return PPC::PRED_GE;
case PPC::PRED_NU: return PPC::PRED_NU;
case PPC::PRED_UN: return PPC::PRED_UN;
case PPC::PRED_EQ_MINUS: return PPC::PRED_EQ_MINUS;
case PPC::PRED_NE_MINUS: return PPC::PRED_NE_MINUS;
case PPC::PRED_LT_MINUS: return PPC::PRED_GT_MINUS;
case PPC::PRED_GE_MINUS: return PPC::PRED_LE_MINUS;
case PPC::PRED_GT_MINUS: return PPC::PRED_LT_MINUS;
case PPC::PRED_LE_MINUS: return PPC::PRED_GE_MINUS;
case PPC::PRED_NU_MINUS: return PPC::PRED_NU_MINUS;
case PPC::PRED_UN_MINUS: return PPC::PRED_UN_MINUS;
case PPC::PRED_EQ_PLUS: return PPC::PRED_EQ_PLUS;
case PPC::PRED_NE_PLUS: return PPC::PRED_NE_PLUS;
case PPC::PRED_LT_PLUS: return PPC::PRED_GT_PLUS;
case PPC::PRED_GE_PLUS: return PPC::PRED_LE_PLUS;
case PPC::PRED_GT_PLUS: return PPC::PRED_LT_PLUS;
case PPC::PRED_LE_PLUS: return PPC::PRED_GE_PLUS;
case PPC::PRED_NU_PLUS: return PPC::PRED_NU_PLUS;
case PPC::PRED_UN_PLUS: return PPC::PRED_UN_PLUS;
}
llvm_unreachable("Unknown PPC branch opcode!");
}

32
lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h
View File

@ -25,14 +25,30 @@ namespace llvm {
namespace PPC {
/// Predicate - These are "(BI << 5) | BO" for various predicates.
enum Predicate {
PRED_LT = (0 << 5) | 12,
PRED_LE = (1 << 5) | 4,
PRED_EQ = (2 << 5) | 12,
PRED_GE = (0 << 5) | 4,
PRED_GT = (1 << 5) | 12,
PRED_NE = (2 << 5) | 4,
PRED_UN = (3 << 5) | 12,
PRED_NU = (3 << 5) | 4
PRED_LT = (0 << 5) | 12,
PRED_LE = (1 << 5) | 4,
PRED_EQ = (2 << 5) | 12,
PRED_GE = (0 << 5) | 4,
PRED_GT = (1 << 5) | 12,
PRED_NE = (2 << 5) | 4,
PRED_UN = (3 << 5) | 12,
PRED_NU = (3 << 5) | 4,
PRED_LT_MINUS = (0 << 5) | 14,
PRED_LE_MINUS = (1 << 5) | 6,
PRED_EQ_MINUS = (2 << 5) | 14,
PRED_GE_MINUS = (0 << 5) | 6,
PRED_GT_MINUS = (1 << 5) | 14,
PRED_NE_MINUS = (2 << 5) | 6,
PRED_UN_MINUS = (3 << 5) | 14,
PRED_NU_MINUS = (3 << 5) | 6,
PRED_LT_PLUS = (0 << 5) | 15,
PRED_LE_PLUS = (1 << 5) | 7,
PRED_EQ_PLUS = (2 << 5) | 15,
PRED_GE_PLUS = (0 << 5) | 7,
PRED_GT_PLUS = (1 << 5) | 15,
PRED_NE_PLUS = (2 << 5) | 7,
PRED_UN_PLUS = (3 << 5) | 15,
PRED_NU_PLUS = (3 << 5) | 7
};
/// Invert the specified predicate. != -> ==, < -> >=.

4
lib/Target/PowerPC/PPCInstr64Bit.td
View File

@ -69,7 +69,7 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
let isCodeGenOnly = 1 in
def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
"b${cond:cc}ctr ${cond:reg}", BrB, []>,
"b${cond:cc}ctr${cond:pm} ${cond:reg}", BrB, []>,
Requires<[In64BitMode]>;
}
}
@ -130,7 +130,7 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
let isCodeGenOnly = 1 in
def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
"b${cond:cc}ctrl ${cond:reg}", BrB, []>,
"b${cond:cc}ctrl${cond:pm} ${cond:reg}", BrB, []>,
Requires<[In64BitMode]>;
}
}

149
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -883,7 +883,7 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
let isCodeGenOnly = 1 in
def BCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
"b${cond:cc}ctr ${cond:reg}", BrB, []>;
"b${cond:cc}ctr${cond:pm} ${cond:reg}", BrB, []>;
}
}
@ -905,21 +905,29 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
// a two-value operand where a dag node expects two operands. :(
let isCodeGenOnly = 1 in {
def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
"b${cond:cc} ${cond:reg}, $dst"
"b${cond:cc}${cond:pm} ${cond:reg}, $dst"
/*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
"b${cond:cc}a ${cond:reg}, $dst">;
"b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
let isReturn = 1, Uses = [LR, RM] in
def BCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
"b${cond:cc}lr ${cond:reg}", BrB, []>;
"b${cond:cc}lr${cond:pm} ${cond:reg}", BrB, []>;
}
let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
"bdzlr", BrB, []>;
def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
"bdnzlr", BrB, []>;
}
def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
"bdzlr+", BrB, []>;
def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
"bdnzlr+", BrB, []>;
def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
"bdzlr-", BrB, []>;
def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
"bdnzlr-", BrB, []>;
}
let Defs = [CTR], Uses = [CTR] in {
@ -931,6 +939,22 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
"bdza $dst">;
def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
"bdnza $dst">;
def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
"bdz+ $dst">;
def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
"bdnz+ $dst">;
def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
"bdza+ $dst">;
def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
"bdnza+ $dst">;
def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
"bdz- $dst">;
def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
"bdnz- $dst">;
def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
"bdza- $dst">;
def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
"bdnza- $dst">;
}
}
@ -952,9 +976,9 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
let isCodeGenOnly = 1 in {
def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
"b${cond:cc}l ${cond:reg}, $dst">;
"b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
"b${cond:cc}la ${cond:reg}, $dst">;
"b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
}
}
let Uses = [CTR, RM] in {
@ -964,7 +988,7 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
let isCodeGenOnly = 1 in
def BCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
"b${cond:cc}ctrl ${cond:reg}", BrB, []>;
"b${cond:cc}ctrl${cond:pm} ${cond:reg}", BrB, []>;
}
let Uses = [LR, RM] in {
def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
@ -972,7 +996,7 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
let isCodeGenOnly = 1 in
def BCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
"b${cond:cc}lrl ${cond:reg}", BrB, []>;
"b${cond:cc}lrl${cond:pm} ${cond:reg}", BrB, []>;
}
let Defs = [CTR], Uses = [CTR, RM] in {
def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
@ -983,12 +1007,36 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
"bdzla $dst">;
def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
"bdnzla $dst">;
def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
"bdzl+ $dst">;
def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
"bdnzl+ $dst">;
def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
"bdzla+ $dst">;
def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
"bdnzla+ $dst">;
def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
"bdzl- $dst">;
def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
"bdnzl- $dst">;
def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
"bdzla- $dst">;
def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
"bdnzla- $dst">;
}
let Defs = [CTR], Uses = [CTR, LR, RM] in {
def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
"bdzlrl", BrB, []>;
def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
"bdnzlrl", BrB, []>;
def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
"bdzlrl+", BrB, []>;
def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
"bdnzlrl+", BrB, []>;
def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
"bdzlrl-", BrB, []>;
def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
"bdnzlrl-", BrB, []>;
}
}
@ -2270,67 +2318,76 @@ def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
multiclass BranchSimpleMnemonic1<string name, int bo> {
def : InstAlias<"b"#name#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
def : InstAlias<"b"#name#"a $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
def : InstAlias<"b"#name#"lr $bi", (gBCLR bo, crbitrc:$bi, 0)>;
def : InstAlias<"b"#name#"l $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
def : InstAlias<"b"#name#"la $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
def : InstAlias<"b"#name#"lrl $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
}
multiclass BranchSimpleMnemonic2<string name, int bo>
: BranchSimpleMnemonic1<name, bo> {
def : InstAlias<"b"#name#"ctr $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
def : InstAlias<"b"#name#"ctrl $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
: BranchSimpleMnemonic1<name, pm, bo> {
def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
}
defm : BranchSimpleMnemonic2<"t", 12>;
defm : BranchSimpleMnemonic2<"f", 4>;
defm : BranchSimpleMnemonic1<"dnzt", 8>;
defm : BranchSimpleMnemonic1<"dnzf", 0>;
defm : BranchSimpleMnemonic1<"dzt", 10>;
defm : BranchSimpleMnemonic1<"dzf", 2>;
defm : BranchSimpleMnemonic2<"t", "", 12>;
defm : BranchSimpleMnemonic2<"f", "", 4>;
defm : BranchSimpleMnemonic2<"t", "-", 14>;
defm : BranchSimpleMnemonic2<"f", "-", 6>;
defm : BranchSimpleMnemonic2<"t", "+", 15>;
defm : BranchSimpleMnemonic2<"f", "+", 7>;
defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
defm : BranchSimpleMnemonic1<"dzt", "", 10>;
defm : BranchSimpleMnemonic1<"dzf", "", 2>;
multiclass BranchExtendedMnemonic<string name, int bibo> {
def : InstAlias<"b"#name#" $cc, $dst",
multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
def : InstAlias<"b"#name#pm#" $cc, $dst",
(BCC bibo, crrc:$cc, condbrtarget:$dst)>;
def : InstAlias<"b"#name#" $dst",
def : InstAlias<"b"#name#pm#" $dst",
(BCC bibo, CR0, condbrtarget:$dst)>;
def : InstAlias<"b"#name#"a $cc, $dst",
def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
(BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
def : InstAlias<"b"#name#"a $dst",
def : InstAlias<"b"#name#"a"#pm#" $dst",
(BCCA bibo, CR0, abscondbrtarget:$dst)>;
def : InstAlias<"b"#name#"lr $cc",
def : InstAlias<"b"#name#"lr"#pm#" $cc",
(BCLR bibo, crrc:$cc)>;
def : InstAlias<"b"#name#"lr",
def : InstAlias<"b"#name#"lr"#pm,
(BCLR bibo, CR0)>;
def : InstAlias<"b"#name#"ctr $cc",
def : InstAlias<"b"#name#"ctr"#pm#" $cc",
(BCCTR bibo, crrc:$cc)>;
def : InstAlias<"b"#name#"ctr",
def : InstAlias<"b"#name#"ctr"#pm,
(BCCTR bibo, CR0)>;
def : InstAlias<"b"#name#"l $cc, $dst",
def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
(BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
def : InstAlias<"b"#name#"l $dst",
def : InstAlias<"b"#name#"l"#pm#" $dst",
(BCCL bibo, CR0, condbrtarget:$dst)>;
def : InstAlias<"b"#name#"la $cc, $dst",
def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
(BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
def : InstAlias<"b"#name#"la $dst",
def : InstAlias<"b"#name#"la"#pm#" $dst",
(BCCLA bibo, CR0, abscondbrtarget:$dst)>;
def : InstAlias<"b"#name#"lrl $cc",
def : InstAlias<"b"#name#"lrl"#pm#" $cc",
(BCLRL bibo, crrc:$cc)>;
def : InstAlias<"b"#name#"lrl",
def : InstAlias<"b"#name#"lrl"#pm,
(BCLRL bibo, CR0)>;
def : InstAlias<"b"#name#"ctrl $cc",
def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
(BCCTRL bibo, crrc:$cc)>;
def : InstAlias<"b"#name#"ctrl",
def : InstAlias<"b"#name#"ctrl"#pm,
(BCCTRL bibo, CR0)>;
}
multiclass BranchExtendedMnemonic<string name, int bibo> {
defm : BranchExtendedMnemonicPM<name, "", bibo>;
defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
}
defm : BranchExtendedMnemonic<"lt", 12>;
defm : BranchExtendedMnemonic<"gt", 44>;
defm : BranchExtendedMnemonic<"eq", 76>;

1136
test/MC/PowerPC/ppc64-encoding-ext.s
View File

File diff suppressed because it is too large Load Diff