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minor tweaks, reject vector preinc.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31717 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-11-14 01:38:31 +00:00
parent c1d6e1fc9c
commit 2fe4bf453b
1 changed files with 9 additions and 4 deletions
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13
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -874,17 +874,22 @@ bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
if (!EnablePPCPreinc) return false;
SDOperand Ptr;
MVT::ValueType VT;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Ptr = LD->getBasePtr();
VT = LD->getValueType(0);
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
ST = ST;
//Ptr = ST->getBasePtr();
//VT = ST->getStoredVT();
// TODO: handle stores.
return false;
Ptr = ST->getBasePtr();
VT = ST->getStoredVT();
return false; // TODO: Stores.
} else
return false;
// PowerPC doesn't have preinc load/store instructions for vectors.
if (MVT::isVector(VT))
return false;
// TODO: Handle reg+reg.
if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
return false;