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fix some funny indentation, add comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43066 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3772,70 +3772,71 @@ SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
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return Result;
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}
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/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
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/// take a 2 x i32 value to shift plus a shift amount.
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SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
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assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
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"Not an i64 shift!");
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bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
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SDOperand ShOpLo = Op.getOperand(0);
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SDOperand ShOpHi = Op.getOperand(1);
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SDOperand ShAmt = Op.getOperand(2);
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SDOperand Tmp1 = isSRA ?
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DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) :
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DAG.getConstant(0, MVT::i32);
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assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
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"Not an i64 shift!");
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bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
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SDOperand ShOpLo = Op.getOperand(0);
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SDOperand ShOpHi = Op.getOperand(1);
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SDOperand ShAmt = Op.getOperand(2);
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SDOperand Tmp1 = isSRA ?
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DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) :
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DAG.getConstant(0, MVT::i32);
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SDOperand Tmp2, Tmp3;
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if (Op.getOpcode() == ISD::SHL_PARTS) {
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Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
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Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
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} else {
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Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
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Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
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}
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SDOperand Tmp2, Tmp3;
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if (Op.getOpcode() == ISD::SHL_PARTS) {
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Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
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Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
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} else {
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Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
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Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
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}
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const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
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SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
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DAG.getConstant(32, MVT::i8));
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SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::i32,
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AndNode, DAG.getConstant(0, MVT::i8));
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const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
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SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
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DAG.getConstant(32, MVT::i8));
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SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::i32,
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AndNode, DAG.getConstant(0, MVT::i8));
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SDOperand Hi, Lo;
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SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
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unsigned Opc = X86ISD::CMOV;
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VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
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SmallVector<SDOperand, 4> Ops;
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if (Op.getOpcode() == ISD::SHL_PARTS) {
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Ops.push_back(Tmp2);
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Ops.push_back(Tmp3);
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Ops.push_back(CC);
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Ops.push_back(Cond);
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Hi = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
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SDOperand Hi, Lo;
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SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
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VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
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SmallVector<SDOperand, 4> Ops;
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if (Op.getOpcode() == ISD::SHL_PARTS) {
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Ops.push_back(Tmp2);
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Ops.push_back(Tmp3);
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Ops.push_back(CC);
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Ops.push_back(Cond);
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Hi = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size());
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Ops.clear();
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Ops.push_back(Tmp3);
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Ops.push_back(Tmp1);
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Ops.push_back(CC);
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Ops.push_back(Cond);
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Lo = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
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} else {
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Ops.push_back(Tmp2);
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Ops.push_back(Tmp3);
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Ops.push_back(CC);
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Ops.push_back(Cond);
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Lo = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
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Ops.clear();
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Ops.push_back(Tmp3);
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Ops.push_back(Tmp1);
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Ops.push_back(CC);
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Ops.push_back(Cond);
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Hi = DAG.getNode(Opc, MVT::i32, &Ops[0], Ops.size());
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}
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VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
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Ops.clear();
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Ops.push_back(Lo);
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Ops.push_back(Hi);
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return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
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Ops.push_back(Tmp3);
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Ops.push_back(Tmp1);
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Ops.push_back(CC);
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Ops.push_back(Cond);
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Lo = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size());
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} else {
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Ops.push_back(Tmp2);
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Ops.push_back(Tmp3);
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Ops.push_back(CC);
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Ops.push_back(Cond);
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Lo = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size());
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Ops.clear();
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Ops.push_back(Tmp3);
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Ops.push_back(Tmp1);
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Ops.push_back(CC);
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Ops.push_back(Cond);
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Hi = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size());
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}
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VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
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Ops.clear();
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Ops.push_back(Lo);
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Ops.push_back(Hi);
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return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
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}
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SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
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