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Add Neon SINT_TO_FP and UINT_TO_FP lowering from v4i16 to v4f32. Fixes

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<rdar://problem/8875309> and <rdar://problem/9057191>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128492 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Cameron Zwarich 2011-03-29 21:41:55 +00:00
parent 6094bd87d8
commit 3007d3331b
2 changed files with 54 additions and 0 deletions
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35
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -461,6 +461,10 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
// Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
// a destination type that is wider than the source.
setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
setTargetDAGCombine(ISD::INTRINSIC_VOID);
setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
@ -2854,8 +2858,39 @@ static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
}
static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
EVT OperandVT = Op.getOperand(0).getValueType();
assert(OperandVT == MVT::v4i16 && "Invalid type for custom lowering!");
if (VT != MVT::v4f32)
return DAG.UnrollVectorOp(Op.getNode());
unsigned CastOpc;
unsigned Opc;
switch (Op.getOpcode()) {
default:
assert(0 && "Invalid opcode!");
case ISD::SINT_TO_FP:
CastOpc = ISD::SIGN_EXTEND;
Opc = ISD::SINT_TO_FP;
break;
case ISD::UINT_TO_FP:
CastOpc = ISD::ZERO_EXTEND;
Opc = ISD::UINT_TO_FP;
break;
}
Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
return DAG.getNode(Opc, dl, VT, Op);
}
static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
EVT VT = Op.getValueType();
if (VT.isVector())
return LowerVectorINT_TO_FP(Op, DAG);
DebugLoc dl = Op.getDebugLoc();
unsigned Opc;

19
test/CodeGen/ARM/int-to-fp.ll Normal file
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@ -0,0 +1,19 @@
; RUN: llc < %s | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
target triple = "thumbv7-apple-darwin10.0.0"
; CHECK: sint_to_fp
; CHECK: vmovl.s16
; CHECK: vcvt.f32.s32
define <4 x float> @sint_to_fp(<4 x i16> %x) nounwind ssp {
%a = sitofp <4 x i16> %x to <4 x float>
ret <4 x float> %a
}
; CHECK: uint_to_fp
; CHECK: vmovl.u16
; CHECK: vcvt.f32.u32
define <4 x float> @uint_to_fp(<4 x i16> %x) nounwind ssp {
%a = uitofp <4 x i16> %x to <4 x float>
ret <4 x float> %a
}