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Fix the post-RA instruction scheduler to handle instructions referenced by
more than one dbg_value instruction. rdar://7759363 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104174 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -225,7 +225,6 @@ namespace llvm {
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private:
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SDNode *Node; // Representative node.
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MachineInstr *Instr; // Alternatively, a MachineInstr.
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MachineInstr *DbgInstr; // A dbg_value referencing this.
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public:
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SUnit *OrigNode; // If not this, the node from which
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// this node was cloned.
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@ -256,6 +255,8 @@ namespace llvm {
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bool isScheduled : 1; // True once scheduled.
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bool isScheduleHigh : 1; // True if preferable to schedule high.
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bool isCloned : 1; // True if this node has been cloned.
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SmallVector<MachineInstr*, 4> DbgInstrList; // dbg_values referencing this.
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private:
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bool isDepthCurrent : 1; // True if Depth is current.
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bool isHeightCurrent : 1; // True if Height is current.
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@ -268,7 +269,7 @@ namespace llvm {
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/// SUnit - Construct an SUnit for pre-regalloc scheduling to represent
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/// an SDNode and any nodes flagged to it.
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SUnit(SDNode *node, unsigned nodenum)
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: Node(node), Instr(0), DbgInstr(0), OrigNode(0), NodeNum(nodenum),
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: Node(node), Instr(0), OrigNode(0), NodeNum(nodenum),
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NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
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NumSuccsLeft(0), isTwoAddress(false), isCommutable(false),
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hasPhysRegDefs(false), hasPhysRegClobbers(false),
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@ -280,7 +281,7 @@ namespace llvm {
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/// SUnit - Construct an SUnit for post-regalloc scheduling to represent
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/// a MachineInstr.
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SUnit(MachineInstr *instr, unsigned nodenum)
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: Node(0), Instr(instr), DbgInstr(0), OrigNode(0), NodeNum(nodenum),
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: Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum),
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NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
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NumSuccsLeft(0), isTwoAddress(false), isCommutable(false),
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hasPhysRegDefs(false), hasPhysRegClobbers(false),
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@ -291,7 +292,7 @@ namespace llvm {
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/// SUnit - Construct a placeholder SUnit.
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SUnit()
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: Node(0), Instr(0), DbgInstr(0), OrigNode(0), NodeNum(~0u),
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: Node(0), Instr(0), OrigNode(0), NodeNum(~0u),
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NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
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NumSuccsLeft(0), isTwoAddress(false), isCommutable(false),
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hasPhysRegDefs(false), hasPhysRegClobbers(false),
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@ -328,20 +329,6 @@ namespace llvm {
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return Instr;
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}
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/// setDbgInstr - Assign the debug instruction for the SUnit.
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/// This may be used during post-regalloc scheduling.
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void setDbgInstr(MachineInstr *MI) {
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assert(!Node && "Setting debug MachineInstr of SUnit with SDNode!");
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DbgInstr = MI;
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}
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/// getDbgInstr - Return the debug MachineInstr for this SUnit.
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/// This may be used during post-regalloc scheduling.
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MachineInstr *getDbgInstr() const {
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assert(!Node && "Reading debug MachineInstr of SUnit with SDNode!");
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return DbgInstr;
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}
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/// addPred - This adds the specified edge as a pred of the current node if
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/// not already. It also adds the current node as a successor of the
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/// specified node.
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@ -210,7 +210,7 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
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assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
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if (MO.isDef() && DanglingDebugValue[Reg].first!=0) {
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SU->setDbgInstr(DanglingDebugValue[Reg].first);
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SU->DbgInstrList.push_back(DanglingDebugValue[Reg].first);
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DbgValueVec[DanglingDebugValue[Reg].second] = 0;
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DanglingDebugValue[Reg] = std::make_pair((MachineInstr*)0, 0);
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}
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@ -599,8 +599,8 @@ MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() {
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}
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BB->insert(InsertPos, SU->getInstr());
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if (SU->getDbgInstr())
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BB->insert(InsertPos, SU->getDbgInstr());
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for (unsigned i = 0, e = SU->DbgInstrList.size() ; i < e ; ++i)
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BB->insert(InsertPos, SU->DbgInstrList[i]);
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}
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// Update the Begin iterator, as the first instruction in the block
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