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Fix the post-RA instruction scheduler to handle instructions referenced by

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more than one dbg_value instruction. rdar://7759363


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104174 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2010-05-19 22:57:06 +00:00
parent e163168aab
commit 309d20c89c
2 changed files with 8 additions and 21 deletions
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6
lib/CodeGen/ScheduleDAGInstrs.cpp
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@@ -210,7 +210,7 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
if (MO.isDef() && DanglingDebugValue[Reg].first!=0) {
SU->setDbgInstr(DanglingDebugValue[Reg].first);
SU->DbgInstrList.push_back(DanglingDebugValue[Reg].first);
DbgValueVec[DanglingDebugValue[Reg].second] = 0;
DanglingDebugValue[Reg] = std::make_pair((MachineInstr*)0, 0);
}
@@ -599,8 +599,8 @@ MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() {
}
BB->insert(InsertPos, SU->getInstr());
if (SU->getDbgInstr())
BB->insert(InsertPos, SU->getDbgInstr());
for (unsigned i = 0, e = SU->DbgInstrList.size() ; i < e ; ++i)
BB->insert(InsertPos, SU->DbgInstrList[i]);
}
// Update the Begin iterator, as the first instruction in the block